/**
 * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
 *
 *  SPDX-License-Identifier: Apache-2.0 OR MIT
 */
#pragma once

// #include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

/** HP_SYSTEM_VER_DATE_REG register
 *  NA
 */
#define HP_SYSTEM_VER_DATE_REG (DR_REG_HP_SYS_BASE + 0x0)
/** HP_SYSTEM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539296770;
 *  NA
 */
#define HP_SYSTEM_REG_VER_DATE    0xFFFFFFFFU
#define HP_SYSTEM_REG_VER_DATE_M  (HP_SYSTEM_REG_VER_DATE_V << HP_SYSTEM_REG_VER_DATE_S)
#define HP_SYSTEM_REG_VER_DATE_V  0xFFFFFFFFU
#define HP_SYSTEM_REG_VER_DATE_S  0

/** HP_SYSTEM_CLK_EN_REG register
 *  NA
 */
#define HP_SYSTEM_CLK_EN_REG (DR_REG_HP_SYS_BASE + 0x4)
/** HP_SYSTEM_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
 *  NA
 */
#define HP_SYSTEM_REG_CLK_EN    (BIT(0))
#define HP_SYSTEM_REG_CLK_EN_M  (HP_SYSTEM_REG_CLK_EN_V << HP_SYSTEM_REG_CLK_EN_S)
#define HP_SYSTEM_REG_CLK_EN_V  0x00000001U
#define HP_SYSTEM_REG_CLK_EN_S  0

/** HP_SYSTEM_CPU_INT_FROM_CPU_0_REG register
 *  NA
 */
#define HP_SYSTEM_CPU_INT_FROM_CPU_0_REG (DR_REG_HP_SYS_BASE + 0x10)
/** HP_SYSTEM_CPU_INT_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
 *  set 1 will trigger a interrupt
 */
#define HP_SYSTEM_CPU_INT_FROM_CPU_0    (BIT(0))
#define HP_SYSTEM_CPU_INT_FROM_CPU_0_M  (HP_SYSTEM_CPU_INT_FROM_CPU_0_V << HP_SYSTEM_CPU_INT_FROM_CPU_0_S)
#define HP_SYSTEM_CPU_INT_FROM_CPU_0_V  0x00000001U
#define HP_SYSTEM_CPU_INT_FROM_CPU_0_S  0

/** HP_SYSTEM_CPU_INT_FROM_CPU_1_REG register
 *  NA
 */
#define HP_SYSTEM_CPU_INT_FROM_CPU_1_REG (DR_REG_HP_SYS_BASE + 0x14)
/** HP_SYSTEM_CPU_INT_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
 *  set 1 will trigger a interrupt
 */
#define HP_SYSTEM_CPU_INT_FROM_CPU_1    (BIT(0))
#define HP_SYSTEM_CPU_INT_FROM_CPU_1_M  (HP_SYSTEM_CPU_INT_FROM_CPU_1_V << HP_SYSTEM_CPU_INT_FROM_CPU_1_S)
#define HP_SYSTEM_CPU_INT_FROM_CPU_1_V  0x00000001U
#define HP_SYSTEM_CPU_INT_FROM_CPU_1_S  0

/** HP_SYSTEM_CPU_INT_FROM_CPU_2_REG register
 *  NA
 */
#define HP_SYSTEM_CPU_INT_FROM_CPU_2_REG (DR_REG_HP_SYS_BASE + 0x18)
/** HP_SYSTEM_CPU_INT_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
 *  set 1 will trigger a interrupt
 */
#define HP_SYSTEM_CPU_INT_FROM_CPU_2    (BIT(0))
#define HP_SYSTEM_CPU_INT_FROM_CPU_2_M  (HP_SYSTEM_CPU_INT_FROM_CPU_2_V << HP_SYSTEM_CPU_INT_FROM_CPU_2_S)
#define HP_SYSTEM_CPU_INT_FROM_CPU_2_V  0x00000001U
#define HP_SYSTEM_CPU_INT_FROM_CPU_2_S  0

/** HP_SYSTEM_CPU_INT_FROM_CPU_3_REG register
 *  NA
 */
#define HP_SYSTEM_CPU_INT_FROM_CPU_3_REG (DR_REG_HP_SYS_BASE + 0x1c)
/** HP_SYSTEM_CPU_INT_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
 *  set 1 will trigger a interrupt
 */
#define HP_SYSTEM_CPU_INT_FROM_CPU_3    (BIT(0))
#define HP_SYSTEM_CPU_INT_FROM_CPU_3_M  (HP_SYSTEM_CPU_INT_FROM_CPU_3_V << HP_SYSTEM_CPU_INT_FROM_CPU_3_S)
#define HP_SYSTEM_CPU_INT_FROM_CPU_3_V  0x00000001U
#define HP_SYSTEM_CPU_INT_FROM_CPU_3_S  0

/** HP_SYSTEM_MODEM_DIAG_EN_REG register
 *  NA
 */
#define HP_SYSTEM_MODEM_DIAG_EN_REG (DR_REG_HP_SYS_BASE + 0x28)
/** HP_SYSTEM_REG_MODEM_DIAG_EN : R/W; bitpos: [31:0]; default: 0;
 *  set reg_modem_diag_en[15:0] will let hp_probe_out[15:0] used as modem_diag[15:0],
 *  set reg_modem_diag_en[31:16] will let lcd_data_out[15:0] used as modem_diag[31:16]
 */
#define HP_SYSTEM_REG_MODEM_DIAG_EN    0xFFFFFFFFU
#define HP_SYSTEM_REG_MODEM_DIAG_EN_M  (HP_SYSTEM_REG_MODEM_DIAG_EN_V << HP_SYSTEM_REG_MODEM_DIAG_EN_S)
#define HP_SYSTEM_REG_MODEM_DIAG_EN_V  0xFFFFFFFFU
#define HP_SYSTEM_REG_MODEM_DIAG_EN_S  0

/** HP_SYSTEM_TCM_RAM_PWR_CTRL0_REG register
 *  NA
 */
#define HP_SYSTEM_TCM_RAM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x3c)
/** HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
 *  hp_tcm clk gatig force on
 */
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON    (BIT(0))
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_S)
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_V  0x00000001U
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_S  0

/** HP_SYSTEM_ROM_PWR_CTRL0_REG register
 *  NA
 */
#define HP_SYSTEM_ROM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x40)
/** HP_SYSTEM_REG_HP_SYSTEM_ROM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
 *  hp_rom clk gating force on
 */
#define HP_SYSTEM_REG_HP_SYSTEM_ROM_CLK_FORCE_ON    (BIT(0))
#define HP_SYSTEM_REG_HP_SYSTEM_ROM_CLK_FORCE_ON_M  (HP_SYSTEM_REG_HP_SYSTEM_ROM_CLK_FORCE_ON_V << HP_SYSTEM_REG_HP_SYSTEM_ROM_CLK_FORCE_ON_S)
#define HP_SYSTEM_REG_HP_SYSTEM_ROM_CLK_FORCE_ON_V  0x00000001U
#define HP_SYSTEM_REG_HP_SYSTEM_ROM_CLK_FORCE_ON_S  0

/** HP_SYSTEM_PROBEA_CTRL_REG register
 *  NA
 */
#define HP_SYSTEM_PROBEA_CTRL_REG (DR_REG_HP_SYS_BASE + 0x50)
/** HP_SYSTEM_REG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
 *  This field is used to selec probe_group from probe_group0 to probe_group15 for
 *  module's probe_out[31:0] in a mode
 */
#define HP_SYSTEM_REG_PROBE_A_MOD_SEL    0x0000FFFFU
#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_M  (HP_SYSTEM_REG_PROBE_A_MOD_SEL_V << HP_SYSTEM_REG_PROBE_A_MOD_SEL_S)
#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_V  0x0000FFFFU
#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_S  0
/** HP_SYSTEM_REG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
 *  This field is used to selec module's probe_out[31:0] as probe out in a mode
 */
#define HP_SYSTEM_REG_PROBE_A_TOP_SEL    0x000000FFU
#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_M  (HP_SYSTEM_REG_PROBE_A_TOP_SEL_V << HP_SYSTEM_REG_PROBE_A_TOP_SEL_S)
#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_V  0x000000FFU
#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_S  16
/** HP_SYSTEM_REG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0;
 *  This field is used to selec probe_out[31:16]
 */
#define HP_SYSTEM_REG_PROBE_L_SEL    0x00000003U
#define HP_SYSTEM_REG_PROBE_L_SEL_M  (HP_SYSTEM_REG_PROBE_L_SEL_V << HP_SYSTEM_REG_PROBE_L_SEL_S)
#define HP_SYSTEM_REG_PROBE_L_SEL_V  0x00000003U
#define HP_SYSTEM_REG_PROBE_L_SEL_S  24
/** HP_SYSTEM_REG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0;
 *  This field is used to selec probe_out[31:16]
 */
#define HP_SYSTEM_REG_PROBE_H_SEL    0x00000003U
#define HP_SYSTEM_REG_PROBE_H_SEL_M  (HP_SYSTEM_REG_PROBE_H_SEL_V << HP_SYSTEM_REG_PROBE_H_SEL_S)
#define HP_SYSTEM_REG_PROBE_H_SEL_V  0x00000003U
#define HP_SYSTEM_REG_PROBE_H_SEL_S  26
/** HP_SYSTEM_REG_PROBE_GLOBAL_EN : R/W; bitpos: [28]; default: 0;
 *  Set this bit to enable global debug probe in hp system.
 */
#define HP_SYSTEM_REG_PROBE_GLOBAL_EN    (BIT(28))
#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_M  (HP_SYSTEM_REG_PROBE_GLOBAL_EN_V << HP_SYSTEM_REG_PROBE_GLOBAL_EN_S)
#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_V  0x00000001U
#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_S  28

/** HP_SYSTEM_PROBEB_CTRL_REG register
 *  NA
 */
#define HP_SYSTEM_PROBEB_CTRL_REG (DR_REG_HP_SYS_BASE + 0x54)
/** HP_SYSTEM_REG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
 *  This field is used to selec probe_group from probe_group0 to probe_group15 for
 *  module's probe_out[31:0] in b mode.
 */
#define HP_SYSTEM_REG_PROBE_B_MOD_SEL    0x0000FFFFU
#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_M  (HP_SYSTEM_REG_PROBE_B_MOD_SEL_V << HP_SYSTEM_REG_PROBE_B_MOD_SEL_S)
#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_V  0x0000FFFFU
#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_S  0
/** HP_SYSTEM_REG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
 *  This field is used to select module's probe_out[31:0]  as probe_out in b mode
 */
#define HP_SYSTEM_REG_PROBE_B_TOP_SEL    0x000000FFU
#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_M  (HP_SYSTEM_REG_PROBE_B_TOP_SEL_V << HP_SYSTEM_REG_PROBE_B_TOP_SEL_S)
#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_V  0x000000FFU
#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_S  16
/** HP_SYSTEM_REG_PROBE_B_EN : R/W; bitpos: [24]; default: 0;
 *  Set this bit to enable b mode for debug probe. 1:  b mode, 0: a mode.
 */
#define HP_SYSTEM_REG_PROBE_B_EN    (BIT(24))
#define HP_SYSTEM_REG_PROBE_B_EN_M  (HP_SYSTEM_REG_PROBE_B_EN_V << HP_SYSTEM_REG_PROBE_B_EN_S)
#define HP_SYSTEM_REG_PROBE_B_EN_V  0x00000001U
#define HP_SYSTEM_REG_PROBE_B_EN_S  24

/** HP_SYSTEM_PROBE_OUT_REG register
 *  NA
 */
#define HP_SYSTEM_PROBE_OUT_REG (DR_REG_HP_SYS_BASE + 0x5c)
/** HP_SYSTEM_REG_PROBE_TOP_OUT : RO; bitpos: [31:0]; default: 0;
 *  NA
 */
#define HP_SYSTEM_REG_PROBE_TOP_OUT    0xFFFFFFFFU
#define HP_SYSTEM_REG_PROBE_TOP_OUT_M  (HP_SYSTEM_REG_PROBE_TOP_OUT_V << HP_SYSTEM_REG_PROBE_TOP_OUT_S)
#define HP_SYSTEM_REG_PROBE_TOP_OUT_V  0xFFFFFFFFU
#define HP_SYSTEM_REG_PROBE_TOP_OUT_S  0

/** HP_SYSTEM_CPU_CORESTALLED_ST_REG register
 *  NA
 */
#define HP_SYSTEM_CPU_CORESTALLED_ST_REG (DR_REG_HP_SYS_BASE + 0x64)
/** HP_SYSTEM_REG_CORE0_CORESTALLED_ST : RO; bitpos: [0]; default: 0;
 *  hp core0 corestalled status
 */
#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST    (BIT(0))
#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_M  (HP_SYSTEM_REG_CORE0_CORESTALLED_ST_V << HP_SYSTEM_REG_CORE0_CORESTALLED_ST_S)
#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_V  0x00000001U
#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_S  0
/** HP_SYSTEM_REG_CORE1_CORESTALLED_ST : RO; bitpos: [1]; default: 0;
 *  hp core1 corestalled status
 */
#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST    (BIT(1))
#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_M  (HP_SYSTEM_REG_CORE1_CORESTALLED_ST_V << HP_SYSTEM_REG_CORE1_CORESTALLED_ST_S)
#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_V  0x00000001U
#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_S  1

/** HP_SYSTEM_CRYPTO_CTRL_REG register
 *  NA
 */
#define HP_SYSTEM_CRYPTO_CTRL_REG (DR_REG_HP_SYS_BASE + 0x70)
/** HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
 *  NA
 */
#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_M  (HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_S)
#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_V  0x00000001U
#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_S  0
/** HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
 *  NA
 */
#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x00000001U
#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
/** HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
 *  NA
 */
#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x00000001U
#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
/** HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
 *  NA
 */
#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3

/** HP_SYSTEM_IOMUX_FPGA_DEBUG_REG register
 *  NA
 */
#define HP_SYSTEM_IOMUX_FPGA_DEBUG_REG (DR_REG_HP_SYS_BASE + 0x7c)
/** HP_SYSTEM_REG_FPGA_DEBUG : R/W; bitpos: [0]; default: 1;
 *  iomux fpga debug
 */
#define HP_SYSTEM_REG_FPGA_DEBUG    (BIT(0))
#define HP_SYSTEM_REG_FPGA_DEBUG_M  (HP_SYSTEM_REG_FPGA_DEBUG_V << HP_SYSTEM_REG_FPGA_DEBUG_S)
#define HP_SYSTEM_REG_FPGA_DEBUG_V  0x00000001U
#define HP_SYSTEM_REG_FPGA_DEBUG_S  0

/** HP_SYSTEM_RDN_ECO_CS_REG register
 *  NA
 */
#define HP_SYSTEM_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0x80)
/** HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
 *  NA
 */
#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN    (BIT(0))
#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_M  (HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_V << HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_S)
#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_V  0x00000001U
#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_S  0
/** HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
 *  NA
 */
#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT    (BIT(1))
#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_M  (HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_V << HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_S)
#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_V  0x00000001U
#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_S  1

/** HP_SYSTEM_TCM_RDN_ECO_CS_REG register
 *  NA
 */
#define HP_SYSTEM_TCM_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0xe4)
/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
 *  NA
 */
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN    (BIT(0))
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_S)
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_V  0x00000001U
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_S  0
/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
 *  NA
 */
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT    (BIT(1))
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_S)
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_V  0x00000001U
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_S  1

/** HP_SYSTEM_TCM_RDN_ECO_LOW_REG register
 *  NA
 */
#define HP_SYSTEM_TCM_RDN_ECO_LOW_REG (DR_REG_HP_SYS_BASE + 0xe8)
/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
 *  NA
 */
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW    0xFFFFFFFFU
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_S)
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_V  0xFFFFFFFFU
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_S  0

/** HP_SYSTEM_TCM_RDN_ECO_HIGH_REG register
 *  NA
 */
#define HP_SYSTEM_TCM_RDN_ECO_HIGH_REG (DR_REG_HP_SYS_BASE + 0xec)
/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
 *  NA
 */
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH    0xFFFFFFFFU
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_S)
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_V  0xFFFFFFFFU
#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_S  0

/** HP_SYSTEM_CACHE_PWR_CTRL_REG register
 *  NA
 */
#define HP_SYSTEM_CACHE_PWR_CTRL_REG (DR_REG_HP_SYS_BASE + 0x110)
/** HP_SYSTEM_REG_AC_MEM_FO : R/W; bitpos: [7:0]; default: 0;
 *  need_des
 */
#define HP_SYSTEM_REG_AC_MEM_FO    0x000000FFU
#define HP_SYSTEM_REG_AC_MEM_FO_M  (HP_SYSTEM_REG_AC_MEM_FO_V << HP_SYSTEM_REG_AC_MEM_FO_S)
#define HP_SYSTEM_REG_AC_MEM_FO_V  0x000000FFU
#define HP_SYSTEM_REG_AC_MEM_FO_S  0
/** HP_SYSTEM_REG_IC_MEM_FO : R/W; bitpos: [15:8]; default: 0;
 *  need_des
 */
#define HP_SYSTEM_REG_IC_MEM_FO    0x000000FFU
#define HP_SYSTEM_REG_IC_MEM_FO_M  (HP_SYSTEM_REG_IC_MEM_FO_V << HP_SYSTEM_REG_IC_MEM_FO_S)
#define HP_SYSTEM_REG_IC_MEM_FO_V  0x000000FFU
#define HP_SYSTEM_REG_IC_MEM_FO_S  8
/** HP_SYSTEM_REG_DC_MEM_FO : R/W; bitpos: [23:16]; default: 0;
 *  need_des
 */
#define HP_SYSTEM_REG_DC_MEM_FO    0x000000FFU
#define HP_SYSTEM_REG_DC_MEM_FO_M  (HP_SYSTEM_REG_DC_MEM_FO_V << HP_SYSTEM_REG_DC_MEM_FO_S)
#define HP_SYSTEM_REG_DC_MEM_FO_V  0x000000FFU
#define HP_SYSTEM_REG_DC_MEM_FO_S  16

/** HP_SYSTEM_TCM_DATA_DUMP_CTRL_REG register
 *  need_des
 */
#define HP_SYSTEM_TCM_DATA_DUMP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x114)
/** HP_SYSTEM_TCM_DATA_DUMP_EN : R/W; bitpos: [31:0]; default: 0;
 *  hp tcm_data dump switch
 */
#define HP_SYSTEM_TCM_DATA_DUMP_EN    0xFFFFFFFFU
#define HP_SYSTEM_TCM_DATA_DUMP_EN_M  (HP_SYSTEM_TCM_DATA_DUMP_EN_V << HP_SYSTEM_TCM_DATA_DUMP_EN_S)
#define HP_SYSTEM_TCM_DATA_DUMP_EN_V  0xFFFFFFFFU
#define HP_SYSTEM_TCM_DATA_DUMP_EN_S  0

/** HP_SYSTEM_CPU_WAITI_CONF_REG register
 *  CPU_WAITI configuration register
 */
#define HP_SYSTEM_CPU_WAITI_CONF_REG (DR_REG_HP_SYS_BASE + 0x118)
/** HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [0]; default: 1;
 *  Set 1 to force cpu_waiti_clk enable.
 */
#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON    (BIT(0))
#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_M  (HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_V << HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_S)
#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_S  0
/** HP_SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [4:1]; default: 0;
 *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
 *  will close
 */
#define HP_SYSTEM_CPU_WAITI_DELAY_NUM    0x0000000FU
#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_M  (HP_SYSTEM_CPU_WAITI_DELAY_NUM_V << HP_SYSTEM_CPU_WAITI_DELAY_NUM_S)
#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_V  0x0000000FU
#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_S  1

/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG register
 *  Core Debug runstall configure register
 */
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYS_BASE + 0x11c)
/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
 *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
 */
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE    (BIT(0))
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_M  (HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S)
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V  0x00000001U
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S  0

/** HP_SYSTEM_CORE_IBUS_TIMEOUT_CONF_REG register
 *  need_des
 */
#define HP_SYSTEM_CORE_IBUS_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x124)
/** HP_SYSTEM_CORE_IBUS_TIMEOUT_PROTECT_EN : R/W; bitpos: [0]; default: 1;
 *  set this field to 1 to enable hp core0&1 ibus timeout handle
 */
#define HP_SYSTEM_CORE_IBUS_TIMEOUT_PROTECT_EN    (BIT(0))
#define HP_SYSTEM_CORE_IBUS_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_CORE_IBUS_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CORE_IBUS_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_CORE_IBUS_TIMEOUT_PROTECT_EN_V  0x00000001U
#define HP_SYSTEM_CORE_IBUS_TIMEOUT_PROTECT_EN_S  0
/** HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
 *  This field used to set hp core0&1 ibus timeout  threshold
 */
#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES    0x0000FFFFU
#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_M  (HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_V << HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_S)
#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_V  0x0000FFFFU
#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_S  1

/** HP_SYSTEM_CORE_DBUS_TIMEOUT_CONF_REG register
 *  need_des
 */
#define HP_SYSTEM_CORE_DBUS_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x128)
/** HP_SYSTEM_CORE_DBUS_TIMEOUT_PROTECT_EN : R/W; bitpos: [0]; default: 1;
 *  set this field to 1 to enable hp core0&1 dbus timeout handle
 */
#define HP_SYSTEM_CORE_DBUS_TIMEOUT_PROTECT_EN    (BIT(0))
#define HP_SYSTEM_CORE_DBUS_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_CORE_DBUS_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CORE_DBUS_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_CORE_DBUS_TIMEOUT_PROTECT_EN_V  0x00000001U
#define HP_SYSTEM_CORE_DBUS_TIMEOUT_PROTECT_EN_S  0
/** HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
 *  This field used to set hp core0&1 dbus timeout  threshold
 */
#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES    0x0000FFFFU
#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_M  (HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_V << HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_S)
#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_V  0x0000FFFFU
#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_S  1

/** HP_SYSTEM_ICM_H2X_CFG_REG register
 *  need_des
 */
#define HP_SYSTEM_ICM_H2X_CFG_REG (DR_REG_HP_SYS_BASE + 0x138)
/** HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN : R/W; bitpos: [0]; default: 0;
 *  need_des
 */
#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN    (BIT(0))
#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_M  (HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_V << HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_S)
#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_V  0x00000001U
#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_S  0
/** HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN : R/W; bitpos: [1]; default: 1;
 *  need_des
 */
#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN    (BIT(1))
#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_M  (HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_V << HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_S)
#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_V  0x00000001U
#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_S  1
/** HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY : RO; bitpos: [2]; default: 0;
 *  need_des
 */
#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY    (BIT(2))
#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_M  (HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_V << HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_S)
#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_V  0x00000001U
#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_S  2
/** HP_SYSTEM_SDMMC_ICM_H2X_POST_WR_EN : R/W; bitpos: [3]; default: 0;
 *  need_des
 */
#define HP_SYSTEM_SDMMC_ICM_H2X_POST_WR_EN    (BIT(3))
#define HP_SYSTEM_SDMMC_ICM_H2X_POST_WR_EN_M  (HP_SYSTEM_SDMMC_ICM_H2X_POST_WR_EN_V << HP_SYSTEM_SDMMC_ICM_H2X_POST_WR_EN_S)
#define HP_SYSTEM_SDMMC_ICM_H2X_POST_WR_EN_V  0x00000001U
#define HP_SYSTEM_SDMMC_ICM_H2X_POST_WR_EN_S  3
/** HP_SYSTEM_SDMMC_ICM_H2X_CUT_THROUGH_EN : R/W; bitpos: [4]; default: 1;
 *  need_des
 */
#define HP_SYSTEM_SDMMC_ICM_H2X_CUT_THROUGH_EN    (BIT(4))
#define HP_SYSTEM_SDMMC_ICM_H2X_CUT_THROUGH_EN_M  (HP_SYSTEM_SDMMC_ICM_H2X_CUT_THROUGH_EN_V << HP_SYSTEM_SDMMC_ICM_H2X_CUT_THROUGH_EN_S)
#define HP_SYSTEM_SDMMC_ICM_H2X_CUT_THROUGH_EN_V  0x00000001U
#define HP_SYSTEM_SDMMC_ICM_H2X_CUT_THROUGH_EN_S  4
/** HP_SYSTEM_SDMMC_ICM_H2X_BRIDGE_BUSY : RO; bitpos: [5]; default: 0;
 *  need_des
 */
#define HP_SYSTEM_SDMMC_ICM_H2X_BRIDGE_BUSY    (BIT(5))
#define HP_SYSTEM_SDMMC_ICM_H2X_BRIDGE_BUSY_M  (HP_SYSTEM_SDMMC_ICM_H2X_BRIDGE_BUSY_V << HP_SYSTEM_SDMMC_ICM_H2X_BRIDGE_BUSY_S)
#define HP_SYSTEM_SDMMC_ICM_H2X_BRIDGE_BUSY_V  0x00000001U
#define HP_SYSTEM_SDMMC_ICM_H2X_BRIDGE_BUSY_S  5

/** HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG register
 *  Bitscrambler Peri Sel
 */
#define HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG (DR_REG_HP_SYS_BASE + 0x140)
/** HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL : R/W; bitpos: [4:0]; default: 0;
 *  Set  this field to sel peri with DMA RX interface to connect with bitscrambler:
 *  lcd_cam: 5'h1, gpspi2: 5'h2: gpspi3: 5'h3, parl_io:5'h4, aes: 5'h5, sha: 5'h6, adc:
 *  5'h7, i2s0_ch0: 5'h8, i2s0_ch1: 5'h9, i2s0_ch2: 5'ha, i2s0_ch3: 5'hb,
 *  i2s1_ch0: 5'hc, i2s1_ch1: 5'hd, i2s1_ch2: 5'he, i2s1_ch3: 5'hf, uhci0: 5'h10, RMT:
 *  5'h11, none: else.
 */
#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL    0x0000001FU
#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_M  (HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_V << HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_S)
#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_V  0x0000001FU
#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_S  0
/** HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL : R/W; bitpos: [9:5]; default: 0;
 *  Set  this field to sel peri with DMA TX interface to connect with bitscrambler:
 *  lcd_cam: 5'h1, gpspi2: 5'h2: gpspi3: 5'h3, parl_io:5'h4, aes: 5'h5, sha: 5'h6, adc:
 *  5'h7, i2s0_ch0: 5'h8, i2s0_ch1: 5'h9, i2s0_ch2: 5'ha, i2s0_ch3: 5'hb,
 *  i2s1_ch0: 5'hc, i2s1_ch1: 5'hd, i2s1_ch2: 5'he, i2s1_ch3: 5'hf, uhci0: 5'h10, RMT:
 *  5'h11, none: else.
 */
#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL    0x0000001FU
#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_M  (HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_V << HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_S)
#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_V  0x0000001FU
#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_S  5

/** HP_SYSTEM_GDMA_CTRL_REG register
 *  N/A
 */
#define HP_SYSTEM_GDMA_CTRL_REG (DR_REG_HP_SYS_BASE + 0x148)
/** HP_SYSTEM_DEBUG_CH_NUM : R/W; bitpos: [1:0]; default: 0;
 *  N/A
 */
#define HP_SYSTEM_DEBUG_CH_NUM    0x00000003U
#define HP_SYSTEM_DEBUG_CH_NUM_M  (HP_SYSTEM_DEBUG_CH_NUM_V << HP_SYSTEM_DEBUG_CH_NUM_S)
#define HP_SYSTEM_DEBUG_CH_NUM_V  0x00000003U
#define HP_SYSTEM_DEBUG_CH_NUM_S  0

/** HP_SYSTEM_VPU_CTRL_REG register
 *  N/A
 */
#define HP_SYSTEM_VPU_CTRL_REG (DR_REG_HP_SYS_BASE + 0x158)
/** HP_SYSTEM_PPA_LSLP_MEM_PD : R/W; bitpos: [0]; default: 0;
 *  N/A
 */
#define HP_SYSTEM_PPA_LSLP_MEM_PD    (BIT(0))
#define HP_SYSTEM_PPA_LSLP_MEM_PD_M  (HP_SYSTEM_PPA_LSLP_MEM_PD_V << HP_SYSTEM_PPA_LSLP_MEM_PD_S)
#define HP_SYSTEM_PPA_LSLP_MEM_PD_V  0x00000001U
#define HP_SYSTEM_PPA_LSLP_MEM_PD_S  0
/** HP_SYSTEM_JPEG_SDSLP_MEM_PD : R/W; bitpos: [1]; default: 0;
 *  N/A
 */
#define HP_SYSTEM_JPEG_SDSLP_MEM_PD    (BIT(1))
#define HP_SYSTEM_JPEG_SDSLP_MEM_PD_M  (HP_SYSTEM_JPEG_SDSLP_MEM_PD_V << HP_SYSTEM_JPEG_SDSLP_MEM_PD_S)
#define HP_SYSTEM_JPEG_SDSLP_MEM_PD_V  0x00000001U
#define HP_SYSTEM_JPEG_SDSLP_MEM_PD_S  1
/** HP_SYSTEM_JPEG_LSLP_MEM_PD : R/W; bitpos: [2]; default: 0;
 *  N/A
 */
#define HP_SYSTEM_JPEG_LSLP_MEM_PD    (BIT(2))
#define HP_SYSTEM_JPEG_LSLP_MEM_PD_M  (HP_SYSTEM_JPEG_LSLP_MEM_PD_V << HP_SYSTEM_JPEG_LSLP_MEM_PD_S)
#define HP_SYSTEM_JPEG_LSLP_MEM_PD_V  0x00000001U
#define HP_SYSTEM_JPEG_LSLP_MEM_PD_S  2
/** HP_SYSTEM_JPEG_DSLP_MEM_PD : R/W; bitpos: [3]; default: 0;
 *  N/A
 */
#define HP_SYSTEM_JPEG_DSLP_MEM_PD    (BIT(3))
#define HP_SYSTEM_JPEG_DSLP_MEM_PD_M  (HP_SYSTEM_JPEG_DSLP_MEM_PD_V << HP_SYSTEM_JPEG_DSLP_MEM_PD_S)
#define HP_SYSTEM_JPEG_DSLP_MEM_PD_V  0x00000001U
#define HP_SYSTEM_JPEG_DSLP_MEM_PD_S  3
/** HP_SYSTEM_DMA2D_LSLP_MEM_PD : R/W; bitpos: [4]; default: 0;
 *  N/A
 */
#define HP_SYSTEM_DMA2D_LSLP_MEM_PD    (BIT(4))
#define HP_SYSTEM_DMA2D_LSLP_MEM_PD_M  (HP_SYSTEM_DMA2D_LSLP_MEM_PD_V << HP_SYSTEM_DMA2D_LSLP_MEM_PD_S)
#define HP_SYSTEM_DMA2D_LSLP_MEM_PD_V  0x00000001U
#define HP_SYSTEM_DMA2D_LSLP_MEM_PD_S  4

/** HP_SYSTEM_DESIGN_FOR_VERIFICATION0_REG register
 *  need_des
 */
#define HP_SYSTEM_DESIGN_FOR_VERIFICATION0_REG (DR_REG_HP_SYS_BASE + 0x170)
/** HP_SYSTEM_DFV0 : R/W; bitpos: [31:0]; default: 0;
 *  register for DV
 */
#define HP_SYSTEM_DFV0    0xFFFFFFFFU
#define HP_SYSTEM_DFV0_M  (HP_SYSTEM_DFV0_V << HP_SYSTEM_DFV0_S)
#define HP_SYSTEM_DFV0_V  0xFFFFFFFFU
#define HP_SYSTEM_DFV0_S  0

/** HP_SYSTEM_DESIGN_FOR_VERIFICATION1_REG register
 *  need_des
 */
#define HP_SYSTEM_DESIGN_FOR_VERIFICATION1_REG (DR_REG_HP_SYS_BASE + 0x174)
/** HP_SYSTEM_DFV1 : R/W; bitpos: [31:0]; default: 0;
 *  register for DV
 */
#define HP_SYSTEM_DFV1    0xFFFFFFFFU
#define HP_SYSTEM_DFV1_M  (HP_SYSTEM_DFV1_V << HP_SYSTEM_DFV1_S)
#define HP_SYSTEM_DFV1_V  0xFFFFFFFFU
#define HP_SYSTEM_DFV1_S  0

/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_RAW_REG register
 *  NA
 */
#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x188)
/** HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
 *  the raw interrupt status of bresp error,  triggered when if  bresp err occurs  in
 *  post write mode in ahb2axi.
 */
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_RAW    (BIT(30))
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_RAW_M  (HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_RAW_V << HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_RAW_S)
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_RAW_V  0x00000001U
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_RAW_S  30
/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
 *  the raw interrupt status of bresp error,  triggered when if  bresp err occurs  in
 *  post write mode in ahb2axi.
 */
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW    (BIT(31))
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_S)
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_V  0x00000001U
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_S  31

/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ST_REG register
 *  need_des
 */
#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x18c)
/** HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ST : RO; bitpos: [30]; default: 0;
 *  the masked interrupt status of  sdmmc_icm_h2x_bresp_err
 */
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ST    (BIT(30))
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ST_M  (HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ST_V << HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ST_S)
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ST_V  0x00000001U
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ST_S  30
/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST : RO; bitpos: [31]; default: 0;
 *  the masked interrupt status of  cpu_icm_h2x_bresp_err
 */
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST    (BIT(31))
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_S)
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_V  0x00000001U
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_S  31

/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ENA_REG register
 *  need_des
 */
#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x190)
/** HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ENA : R/W; bitpos: [30]; default: 0;
 *  Write 1 to enable sdmmc_icm_h2x_bresp_err int
 */
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ENA    (BIT(30))
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ENA_M  (HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ENA_V << HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ENA_S)
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ENA_V  0x00000001U
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ENA_S  30
/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA : R/W; bitpos: [31]; default: 0;
 *  Write 1 to enable cpu_icm_h2x_bresp_err int
 */
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA    (BIT(31))
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_S)
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_V  0x00000001U
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_S  31

/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_CLR_REG register
 *  need_des
 */
#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x194)
/** HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_CLR : WT; bitpos: [30]; default: 0;
 *  Write 1 to clear sdmmc_icm_h2x_bresp_err  int
 */
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_CLR    (BIT(30))
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_CLR_M  (HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_CLR_V << HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_CLR_S)
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_CLR_V  0x00000001U
#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_CLR_S  30
/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR : WT; bitpos: [31]; default: 0;
 *  Write 1 to clear cpu_icm_h2x_bresp_err  int
 */
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR    (BIT(31))
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_S)
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_V  0x00000001U
#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_S  31

/** HP_SYSTEM_CORE_DMACTIVE_LPCORE_REG register
 *  need_des
 */
#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_REG (DR_REG_HP_SYS_BASE + 0x1a0)
/** HP_SYSTEM_CORE_DMACTIVE_LPCORE : RO; bitpos: [0]; default: 0;
 *  hp core dmactive_lpcore value
 */
#define HP_SYSTEM_CORE_DMACTIVE_LPCORE    (BIT(0))
#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_M  (HP_SYSTEM_CORE_DMACTIVE_LPCORE_V << HP_SYSTEM_CORE_DMACTIVE_LPCORE_S)
#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_V  0x00000001U
#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_S  0

/** HP_SYSTEM_CORE_ERR_RESP_DIS_REG register
 *  need_des
 */
#define HP_SYSTEM_CORE_ERR_RESP_DIS_REG (DR_REG_HP_SYS_BASE + 0x1a4)
/** HP_SYSTEM_CORE_ERR_RESP_DIS : R/W; bitpos: [2:0]; default: 0;
 *  Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp.  Set bit 2 to
 *  disable ahb err resp.
 */
#define HP_SYSTEM_CORE_ERR_RESP_DIS    0x00000007U
#define HP_SYSTEM_CORE_ERR_RESP_DIS_M  (HP_SYSTEM_CORE_ERR_RESP_DIS_V << HP_SYSTEM_CORE_ERR_RESP_DIS_S)
#define HP_SYSTEM_CORE_ERR_RESP_DIS_V  0x00000007U
#define HP_SYSTEM_CORE_ERR_RESP_DIS_S  0

/** HP_SYSTEM_CORE_TIMEOUT_INT_RAW_REG register
 *  Hp core bus timeout interrupt raw register
 */
#define HP_SYSTEM_CORE_TIMEOUT_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x1a8)
/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
 *  the raw interrupt status of hp core0  ibus timeout
 */
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW    (BIT(2))
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_S)
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_S  2
/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
 *  the raw interrupt status of hp core1  ibus timeout
 */
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW    (BIT(3))
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_S)
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_S  3
/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
 *  the raw interrupt status of hp core0  dbus timeout
 */
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW    (BIT(4))
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_S)
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_S  4
/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
 *  the raw interrupt status of hp core1  dbus timeout
 */
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW    (BIT(5))
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_S)
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_S  5

/** HP_SYSTEM_CORE_TIMEOUT_INT_ST_REG register
 *  masked interrupt register
 */
#define HP_SYSTEM_CORE_TIMEOUT_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x1ac)
/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST : RO; bitpos: [2]; default: 0;
 *  the masked interrupt status of hp core0  ibus timeout
 */
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST    (BIT(2))
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_S)
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_V  0x00000001U
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_S  2
/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST : RO; bitpos: [3]; default: 0;
 *  the masked interrupt status of hp core1  ibus timeout
 */
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST    (BIT(3))
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_S)
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_V  0x00000001U
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_S  3
/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
 *  the masked interrupt status of hp core0  dbus timeout
 */
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST    (BIT(4))
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_S)
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_V  0x00000001U
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_S  4
/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST : RO; bitpos: [5]; default: 0;
 *  the masked interrupt status of hp core1  dbus timeout
 */
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST    (BIT(5))
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_S)
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_V  0x00000001U
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_S  5

/** HP_SYSTEM_CORE_TIMEOUT_INT_ENA_REG register
 *  masked interrupt register
 */
#define HP_SYSTEM_CORE_TIMEOUT_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x1b0)
/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [2]; default: 0;
 *  Write 1 to enable hp_core0_ibus_timeout int
 */
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA    (BIT(2))
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_S)
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_S  2
/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [3]; default: 0;
 *  Write 1 to enable hp_core1_ibus_timeout int
 */
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA    (BIT(3))
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_S)
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_S  3
/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
 *  Write 1 to enable hp_core0_dbus_timeout int
 */
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA    (BIT(4))
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_S)
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_S  4
/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [5]; default: 0;
 *  Write 1 to enable hp_core1_dbus_timeout int
 */
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA    (BIT(5))
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_S)
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_S  5

/** HP_SYSTEM_CORE_TIMEOUT_INT_CLR_REG register
 *  interrupt clear register
 */
#define HP_SYSTEM_CORE_TIMEOUT_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x1b4)
/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [2]; default: 0;
 *  Write 1 to clear hp_core0_ibus_timeout int
 */
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR    (BIT(2))
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_S)
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_S  2
/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [3]; default: 0;
 *  Write 1 to clear hp_core1_ibus_timeout int
 */
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR    (BIT(3))
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_S)
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_S  3
/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
 *  Write 1 to clear hp_core0_dbus_timeout int
 */
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR    (BIT(4))
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_S)
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_S  4
/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [5]; default: 0;
 *  Write 1 to clear hp_core1_dbus_timeout int
 */
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR    (BIT(5))
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_S)
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_S  5

/** HP_SYSTEM_CORE_PAD_WAKEUP_EVENT_REG register
 *  pad wakeup event register
 */
#define HP_SYSTEM_CORE_PAD_WAKEUP_EVENT_REG (DR_REG_HP_SYS_BASE + 0x1b8)
/** HP_SYSTEM_CORE0_PAD_WAKEUP_EVENT : R/W; bitpos: [0]; default: 0;
 *  wakeup core0 register
 */
#define HP_SYSTEM_CORE0_PAD_WAKEUP_EVENT    (BIT(0))
#define HP_SYSTEM_CORE0_PAD_WAKEUP_EVENT_M  (HP_SYSTEM_CORE0_PAD_WAKEUP_EVENT_V << HP_SYSTEM_CORE0_PAD_WAKEUP_EVENT_S)
#define HP_SYSTEM_CORE0_PAD_WAKEUP_EVENT_V  0x00000001U
#define HP_SYSTEM_CORE0_PAD_WAKEUP_EVENT_S  0
/** HP_SYSTEM_CORE1_PAD_WAKEUP_EVENT : R/W; bitpos: [1]; default: 0;
 *  wakeup core1 register
 */
#define HP_SYSTEM_CORE1_PAD_WAKEUP_EVENT    (BIT(1))
#define HP_SYSTEM_CORE1_PAD_WAKEUP_EVENT_M  (HP_SYSTEM_CORE1_PAD_WAKEUP_EVENT_V << HP_SYSTEM_CORE1_PAD_WAKEUP_EVENT_S)
#define HP_SYSTEM_CORE1_PAD_WAKEUP_EVENT_V  0x00000001U
#define HP_SYSTEM_CORE1_PAD_WAKEUP_EVENT_S  1

/** HP_SYSTEM_TWAI0_TIMESTAMP_L_REG register
 *  twai0 timestamp low bit reg
 */
#define HP_SYSTEM_TWAI0_TIMESTAMP_L_REG (DR_REG_HP_SYS_BASE + 0x1c0)
/** HP_SYSTEM_TWAI0_TIMESTAMP_I : R/W; bitpos: [31:0]; default: 4294967295;
 *  This field used to set lower 32bits of timestamp hp twai0
 */
#define HP_SYSTEM_TWAI0_TIMESTAMP_I    0xFFFFFFFFU
#define HP_SYSTEM_TWAI0_TIMESTAMP_I_M  (HP_SYSTEM_TWAI0_TIMESTAMP_I_V << HP_SYSTEM_TWAI0_TIMESTAMP_I_S)
#define HP_SYSTEM_TWAI0_TIMESTAMP_I_V  0xFFFFFFFFU
#define HP_SYSTEM_TWAI0_TIMESTAMP_I_S  0

/** HP_SYSTEM_TWAI0_TIMESTAMP_H_REG register
 *  twai0 timestamp high bit reg
 */
#define HP_SYSTEM_TWAI0_TIMESTAMP_H_REG (DR_REG_HP_SYS_BASE + 0x1c4)
/** HP_SYSTEM_TWAI0_TIMESTAMP_H : R/W; bitpos: [31:0]; default: 4294967295;
 *  This field used to set upper 32bits of timestamp hp twai0
 */
#define HP_SYSTEM_TWAI0_TIMESTAMP_H    0xFFFFFFFFU
#define HP_SYSTEM_TWAI0_TIMESTAMP_H_M  (HP_SYSTEM_TWAI0_TIMESTAMP_H_V << HP_SYSTEM_TWAI0_TIMESTAMP_H_S)
#define HP_SYSTEM_TWAI0_TIMESTAMP_H_V  0xFFFFFFFFU
#define HP_SYSTEM_TWAI0_TIMESTAMP_H_S  0

/** HP_SYSTEM_TWAI1_TIMESTAMP_L_REG register
 *  twai1 timestamp low bit reg
 */
#define HP_SYSTEM_TWAI1_TIMESTAMP_L_REG (DR_REG_HP_SYS_BASE + 0x1c8)
/** HP_SYSTEM_TWAI1_TIMESTAMP_I : R/W; bitpos: [31:0]; default: 4294967295;
 *  This field used to set lower 32bits of timestamp hp twai1
 */
#define HP_SYSTEM_TWAI1_TIMESTAMP_I    0xFFFFFFFFU
#define HP_SYSTEM_TWAI1_TIMESTAMP_I_M  (HP_SYSTEM_TWAI1_TIMESTAMP_I_V << HP_SYSTEM_TWAI1_TIMESTAMP_I_S)
#define HP_SYSTEM_TWAI1_TIMESTAMP_I_V  0xFFFFFFFFU
#define HP_SYSTEM_TWAI1_TIMESTAMP_I_S  0

/** HP_SYSTEM_TWAI1_TIMESTAMP_H_REG register
 *  twai1 timestamp high bit reg
 */
#define HP_SYSTEM_TWAI1_TIMESTAMP_H_REG (DR_REG_HP_SYS_BASE + 0x1cc)
/** HP_SYSTEM_TWAI1_TIMESTAMP_H : R/W; bitpos: [31:0]; default: 4294967295;
 *  This field used to set upper 32bits of timestamp hp twai1
 */
#define HP_SYSTEM_TWAI1_TIMESTAMP_H    0xFFFFFFFFU
#define HP_SYSTEM_TWAI1_TIMESTAMP_H_M  (HP_SYSTEM_TWAI1_TIMESTAMP_H_V << HP_SYSTEM_TWAI1_TIMESTAMP_H_S)
#define HP_SYSTEM_TWAI1_TIMESTAMP_H_V  0xFFFFFFFFU
#define HP_SYSTEM_TWAI1_TIMESTAMP_H_S  0

/** HP_SYSTEM_RNG_CFG_REG register
 *  rng cfg register
 */
#define HP_SYSTEM_RNG_CFG_REG (DR_REG_HP_SYS_BASE + 0x1d8)
/** HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 0;
 *  chain clk div num to pad for debug
 */
#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM    0x000000FFU
#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_M  (HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_V << HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_S)
#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_V  0x000000FFU
#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_S  16

/** HP_SYSTEM_PERI_MEM_CLK_FORCE_ON_REG register
 *  hp peri mem clk force on regpster
 */
#define HP_SYSTEM_PERI_MEM_CLK_FORCE_ON_REG (DR_REG_HP_SYS_BASE + 0x1e0)
/** HP_SYSTEM_RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
 *  Set this bit to force on mem clk in rmt
 */
#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON    (BIT(0))
#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_V << HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_S)
#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_V  0x00000001U
#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_S  0
/** HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
 *  Set this bit to force on tx mem clk in bitscrambler
 */
#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON    (BIT(1))
#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_V << HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_S)
#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_V  0x00000001U
#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_S  1
/** HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON : R/W; bitpos: [2]; default: 0;
 *  Set this bit to force on rx mem clk in bitscrambler
 */
#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON    (BIT(2))
#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_V << HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_S)
#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_V  0x00000001U
#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_S  2
/** HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force on mem clk in gdma
 */
#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON    (BIT(3))
#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_V << HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_S)
#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_V  0x00000001U
#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_S  3

/** HP_SYSTEM_PRDYN_ST_REG register
 *  hp system prdyn status register
 */
#define HP_SYSTEM_PRDYN_ST_REG (DR_REG_HP_SYS_BASE + 0x1e8)
/** HP_SYSTEM_ROM_PRDYN : RO; bitpos: [1]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_ROM_PRDYN    (BIT(1))
#define HP_SYSTEM_ROM_PRDYN_M  (HP_SYSTEM_ROM_PRDYN_V << HP_SYSTEM_ROM_PRDYN_S)
#define HP_SYSTEM_ROM_PRDYN_V  0x00000001U
#define HP_SYSTEM_ROM_PRDYN_S  1
/** HP_SYSTEM_CPU_MEM_PRDYN : RO; bitpos: [3]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_CPU_MEM_PRDYN    (BIT(3))
#define HP_SYSTEM_CPU_MEM_PRDYN_M  (HP_SYSTEM_CPU_MEM_PRDYN_V << HP_SYSTEM_CPU_MEM_PRDYN_S)
#define HP_SYSTEM_CPU_MEM_PRDYN_V  0x00000001U
#define HP_SYSTEM_CPU_MEM_PRDYN_S  3
/** HP_SYSTEM_BITSCRAMBLER_MEM_PRDYN : RO; bitpos: [4]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_BITSCRAMBLER_MEM_PRDYN    (BIT(4))
#define HP_SYSTEM_BITSCRAMBLER_MEM_PRDYN_M  (HP_SYSTEM_BITSCRAMBLER_MEM_PRDYN_V << HP_SYSTEM_BITSCRAMBLER_MEM_PRDYN_S)
#define HP_SYSTEM_BITSCRAMBLER_MEM_PRDYN_V  0x00000001U
#define HP_SYSTEM_BITSCRAMBLER_MEM_PRDYN_S  4
/** HP_SYSTEM_USB_MEM_PRDYN : RO; bitpos: [6]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_USB_MEM_PRDYN    (BIT(6))
#define HP_SYSTEM_USB_MEM_PRDYN_M  (HP_SYSTEM_USB_MEM_PRDYN_V << HP_SYSTEM_USB_MEM_PRDYN_S)
#define HP_SYSTEM_USB_MEM_PRDYN_V  0x00000001U
#define HP_SYSTEM_USB_MEM_PRDYN_S  6
/** HP_SYSTEM_RMT_MEM_PRDYN : RO; bitpos: [7]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_RMT_MEM_PRDYN    (BIT(7))
#define HP_SYSTEM_RMT_MEM_PRDYN_M  (HP_SYSTEM_RMT_MEM_PRDYN_V << HP_SYSTEM_RMT_MEM_PRDYN_S)
#define HP_SYSTEM_RMT_MEM_PRDYN_V  0x00000001U
#define HP_SYSTEM_RMT_MEM_PRDYN_S  7
/** HP_SYSTEM_LEDC0_MEM_PRDYN : RO; bitpos: [8]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_LEDC0_MEM_PRDYN    (BIT(8))
#define HP_SYSTEM_LEDC0_MEM_PRDYN_M  (HP_SYSTEM_LEDC0_MEM_PRDYN_V << HP_SYSTEM_LEDC0_MEM_PRDYN_S)
#define HP_SYSTEM_LEDC0_MEM_PRDYN_V  0x00000001U
#define HP_SYSTEM_LEDC0_MEM_PRDYN_S  8
/** HP_SYSTEM_KEY_MANAGER_MEM_PRDYN : RO; bitpos: [9]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_KEY_MANAGER_MEM_PRDYN    (BIT(9))
#define HP_SYSTEM_KEY_MANAGER_MEM_PRDYN_M  (HP_SYSTEM_KEY_MANAGER_MEM_PRDYN_V << HP_SYSTEM_KEY_MANAGER_MEM_PRDYN_S)
#define HP_SYSTEM_KEY_MANAGER_MEM_PRDYN_V  0x00000001U
#define HP_SYSTEM_KEY_MANAGER_MEM_PRDYN_S  9
/** HP_SYSTEM_VPU_MEM_PRDYN : RO; bitpos: [10]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_VPU_MEM_PRDYN    (BIT(10))
#define HP_SYSTEM_VPU_MEM_PRDYN_M  (HP_SYSTEM_VPU_MEM_PRDYN_V << HP_SYSTEM_VPU_MEM_PRDYN_S)
#define HP_SYSTEM_VPU_MEM_PRDYN_V  0x00000001U
#define HP_SYSTEM_VPU_MEM_PRDYN_S  10
/** HP_SYSTEM_GDMA_MEM_PRDYN : RO; bitpos: [12]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_GDMA_MEM_PRDYN    (BIT(12))
#define HP_SYSTEM_GDMA_MEM_PRDYN_M  (HP_SYSTEM_GDMA_MEM_PRDYN_V << HP_SYSTEM_GDMA_MEM_PRDYN_S)
#define HP_SYSTEM_GDMA_MEM_PRDYN_V  0x00000001U
#define HP_SYSTEM_GDMA_MEM_PRDYN_S  12
/** HP_SYSTEM_UART_MEM_PRDYN : RO; bitpos: [14]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_UART_MEM_PRDYN    (BIT(14))
#define HP_SYSTEM_UART_MEM_PRDYN_M  (HP_SYSTEM_UART_MEM_PRDYN_V << HP_SYSTEM_UART_MEM_PRDYN_S)
#define HP_SYSTEM_UART_MEM_PRDYN_V  0x00000001U
#define HP_SYSTEM_UART_MEM_PRDYN_S  14
/** HP_SYSTEM_CRYPTO_MEM_PRDYN : RO; bitpos: [15]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_CRYPTO_MEM_PRDYN    (BIT(15))
#define HP_SYSTEM_CRYPTO_MEM_PRDYN_M  (HP_SYSTEM_CRYPTO_MEM_PRDYN_V << HP_SYSTEM_CRYPTO_MEM_PRDYN_S)
#define HP_SYSTEM_CRYPTO_MEM_PRDYN_V  0x00000001U
#define HP_SYSTEM_CRYPTO_MEM_PRDYN_S  15
/** HP_SYSTEM_FLASH_MSPI_MEM_PRDYN : RO; bitpos: [16]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_FLASH_MSPI_MEM_PRDYN    (BIT(16))
#define HP_SYSTEM_FLASH_MSPI_MEM_PRDYN_M  (HP_SYSTEM_FLASH_MSPI_MEM_PRDYN_V << HP_SYSTEM_FLASH_MSPI_MEM_PRDYN_S)
#define HP_SYSTEM_FLASH_MSPI_MEM_PRDYN_V  0x00000001U
#define HP_SYSTEM_FLASH_MSPI_MEM_PRDYN_S  16
/** HP_SYSTEM_PSRAM_MSPI_MEM_PRDYN : RO; bitpos: [17]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_PSRAM_MSPI_MEM_PRDYN    (BIT(17))
#define HP_SYSTEM_PSRAM_MSPI_MEM_PRDYN_M  (HP_SYSTEM_PSRAM_MSPI_MEM_PRDYN_V << HP_SYSTEM_PSRAM_MSPI_MEM_PRDYN_S)
#define HP_SYSTEM_PSRAM_MSPI_MEM_PRDYN_V  0x00000001U
#define HP_SYSTEM_PSRAM_MSPI_MEM_PRDYN_S  17
/** HP_SYSTEM_MODEM_MEM_PRDYN : RO; bitpos: [18]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_MODEM_MEM_PRDYN    (BIT(18))
#define HP_SYSTEM_MODEM_MEM_PRDYN_M  (HP_SYSTEM_MODEM_MEM_PRDYN_V << HP_SYSTEM_MODEM_MEM_PRDYN_S)
#define HP_SYSTEM_MODEM_MEM_PRDYN_V  0x00000001U
#define HP_SYSTEM_MODEM_MEM_PRDYN_S  18
/** HP_SYSTEM_LEDC1_MEM_PRDYN : RO; bitpos: [19]; default: 1;
 *  record memory power status
 */
#define HP_SYSTEM_LEDC1_MEM_PRDYN    (BIT(19))
#define HP_SYSTEM_LEDC1_MEM_PRDYN_M  (HP_SYSTEM_LEDC1_MEM_PRDYN_V << HP_SYSTEM_LEDC1_MEM_PRDYN_S)
#define HP_SYSTEM_LEDC1_MEM_PRDYN_V  0x00000001U
#define HP_SYSTEM_LEDC1_MEM_PRDYN_S  19

/** HP_SYSTEM_ICM_CFG_REG register
 *  hp system axi icm ctrl register
 */
#define HP_SYSTEM_ICM_CFG_REG (DR_REG_HP_SYS_BASE + 0x1ec)
/** HP_SYSTEM_ICM_DIS_RD : R/W; bitpos: [2:0]; default: 0;
 *  0:mean master can access slave , 1:mean master can not rd slave ,will returen
 *  decerro on axi bus
 */
#define HP_SYSTEM_ICM_DIS_RD    0x00000007U
#define HP_SYSTEM_ICM_DIS_RD_M  (HP_SYSTEM_ICM_DIS_RD_V << HP_SYSTEM_ICM_DIS_RD_S)
#define HP_SYSTEM_ICM_DIS_RD_V  0x00000007U
#define HP_SYSTEM_ICM_DIS_RD_S  0
/** HP_SYSTEM_ICM_DIS_WR : R/W; bitpos: [5:3]; default: 0;
 *  0:mean master can access slave , 1:mean master can not wr slave ,will returen
 *  decerro on axi bus
 */
#define HP_SYSTEM_ICM_DIS_WR    0x00000007U
#define HP_SYSTEM_ICM_DIS_WR_M  (HP_SYSTEM_ICM_DIS_WR_V << HP_SYSTEM_ICM_DIS_WR_S)
#define HP_SYSTEM_ICM_DIS_WR_V  0x00000007U
#define HP_SYSTEM_ICM_DIS_WR_S  3
/** HP_SYSTEM_ICM_CFG_SECURE : R/W; bitpos: [8:6]; default: 0;
 *  axi_matrix slave ,0: non-secure, 1: secure , total 3 slave.
 */
#define HP_SYSTEM_ICM_CFG_SECURE    0x00000007U
#define HP_SYSTEM_ICM_CFG_SECURE_M  (HP_SYSTEM_ICM_CFG_SECURE_V << HP_SYSTEM_ICM_CFG_SECURE_S)
#define HP_SYSTEM_ICM_CFG_SECURE_V  0x00000007U
#define HP_SYSTEM_ICM_CFG_SECURE_S  6

/** HP_SYSTEM_UART3_MEM_LP_CTRL_REG register
 *  uart memory power control register
 */
#define HP_SYSTEM_UART3_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x1f0)
/** HP_SYSTEM_UART3_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures uart3 memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_UART3_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_UART3_MEM_LP_MODE_M  (HP_SYSTEM_UART3_MEM_LP_MODE_V << HP_SYSTEM_UART3_MEM_LP_MODE_S)
#define HP_SYSTEM_UART3_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_UART3_MEM_LP_MODE_S  0
/** HP_SYSTEM_UART3_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit to power down uart3 memory.
 */
#define HP_SYSTEM_UART3_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_UART3_MEM_LP_EN_M  (HP_SYSTEM_UART3_MEM_LP_EN_V << HP_SYSTEM_UART3_MEM_LP_EN_S)
#define HP_SYSTEM_UART3_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_UART3_MEM_LP_EN_S  2
/** HP_SYSTEM_UART3_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control uart3 memory, disable hardware control.
 */
#define HP_SYSTEM_UART3_MEM_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_UART3_MEM_FORCE_CTRL_M  (HP_SYSTEM_UART3_MEM_FORCE_CTRL_V << HP_SYSTEM_UART3_MEM_FORCE_CTRL_S)
#define HP_SYSTEM_UART3_MEM_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_UART3_MEM_FORCE_CTRL_S  3

/** HP_SYSTEM_RMT_MEM_LP_CTRL_REG register
 *  rmt memory power control register
 */
#define HP_SYSTEM_RMT_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x204)
/** HP_SYSTEM_RMT_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures rmt memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_RMT_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_RMT_MEM_LP_MODE_M  (HP_SYSTEM_RMT_MEM_LP_MODE_V << HP_SYSTEM_RMT_MEM_LP_MODE_S)
#define HP_SYSTEM_RMT_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_RMT_MEM_LP_MODE_S  0
/** HP_SYSTEM_RMT_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit to power down rmt memory.
 */
#define HP_SYSTEM_RMT_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_RMT_MEM_LP_EN_M  (HP_SYSTEM_RMT_MEM_LP_EN_V << HP_SYSTEM_RMT_MEM_LP_EN_S)
#define HP_SYSTEM_RMT_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_RMT_MEM_LP_EN_S  2
/** HP_SYSTEM_RMT_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control rmt memory, disable hardware control.
 */
#define HP_SYSTEM_RMT_MEM_LP_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_RMT_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_RMT_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_RMT_MEM_LP_FORCE_CTRL_S)
#define HP_SYSTEM_RMT_MEM_LP_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_RMT_MEM_LP_FORCE_CTRL_S  3

/** HP_SYSTEM_LEDC0_MEM_LP_CTRL_REG register
 *  ledc0 memory power control register
 */
#define HP_SYSTEM_LEDC0_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x208)
/** HP_SYSTEM_LEDC0_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures ledc0 memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_LEDC0_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_LEDC0_MEM_LP_MODE_M  (HP_SYSTEM_LEDC0_MEM_LP_MODE_V << HP_SYSTEM_LEDC0_MEM_LP_MODE_S)
#define HP_SYSTEM_LEDC0_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_LEDC0_MEM_LP_MODE_S  0
/** HP_SYSTEM_LEDC0_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit to power down ledc0 memory.
 */
#define HP_SYSTEM_LEDC0_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_LEDC0_MEM_LP_EN_M  (HP_SYSTEM_LEDC0_MEM_LP_EN_V << HP_SYSTEM_LEDC0_MEM_LP_EN_S)
#define HP_SYSTEM_LEDC0_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_LEDC0_MEM_LP_EN_S  2
/** HP_SYSTEM_LEDC0_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control ledc0 memory, disable hardware control.
 */
#define HP_SYSTEM_LEDC0_MEM_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_LEDC0_MEM_FORCE_CTRL_M  (HP_SYSTEM_LEDC0_MEM_FORCE_CTRL_V << HP_SYSTEM_LEDC0_MEM_FORCE_CTRL_S)
#define HP_SYSTEM_LEDC0_MEM_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_LEDC0_MEM_FORCE_CTRL_S  3

/** HP_SYSTEM_KM_MEM_LP_CTRL_REG register
 *  key manager memory power control register
 */
#define HP_SYSTEM_KM_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x20c)
/** HP_SYSTEM_KM_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures km memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_KM_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_KM_MEM_LP_MODE_M  (HP_SYSTEM_KM_MEM_LP_MODE_V << HP_SYSTEM_KM_MEM_LP_MODE_S)
#define HP_SYSTEM_KM_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_KM_MEM_LP_MODE_S  0
/** HP_SYSTEM_KM_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
 *  Set this bit to power down km memory.
 */
#define HP_SYSTEM_KM_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_KM_MEM_LP_EN_M  (HP_SYSTEM_KM_MEM_LP_EN_V << HP_SYSTEM_KM_MEM_LP_EN_S)
#define HP_SYSTEM_KM_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_KM_MEM_LP_EN_S  2
/** HP_SYSTEM_KM_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control km memory, disable hardware control.
 */
#define HP_SYSTEM_KM_MEM_LP_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_KM_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_KM_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_KM_MEM_LP_FORCE_CTRL_S)
#define HP_SYSTEM_KM_MEM_LP_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_KM_MEM_LP_FORCE_CTRL_S  3

/** HP_SYSTEM_DMA2D_MEM_LP_CTRL_REG register
 *  vpu memory power control register
 */
#define HP_SYSTEM_DMA2D_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x210)
/** HP_SYSTEM_2DDMA_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures 2ddma memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_2DDMA_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_2DDMA_MEM_LP_MODE_M  (HP_SYSTEM_2DDMA_MEM_LP_MODE_V << HP_SYSTEM_2DDMA_MEM_LP_MODE_S)
#define HP_SYSTEM_2DDMA_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_2DDMA_MEM_LP_MODE_S  0
/** HP_SYSTEM_2DDMA_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit to power down 2ddma memory.
 */
#define HP_SYSTEM_2DDMA_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_2DDMA_MEM_LP_EN_M  (HP_SYSTEM_2DDMA_MEM_LP_EN_V << HP_SYSTEM_2DDMA_MEM_LP_EN_S)
#define HP_SYSTEM_2DDMA_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_2DDMA_MEM_LP_EN_S  2
/** HP_SYSTEM_2DDMA_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control 2ddma memory, disable hardware control.
 */
#define HP_SYSTEM_2DDMA_MEM_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_2DDMA_MEM_FORCE_CTRL_M  (HP_SYSTEM_2DDMA_MEM_FORCE_CTRL_V << HP_SYSTEM_2DDMA_MEM_FORCE_CTRL_S)
#define HP_SYSTEM_2DDMA_MEM_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_2DDMA_MEM_FORCE_CTRL_S  3

/** HP_SYSTEM_AXI_PDMA_MEM_LP_CTRL_REG register
 *  vpu memory power control register
 */
#define HP_SYSTEM_AXI_PDMA_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x214)
/** HP_SYSTEM_AXI_PDMA_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
 *  Configures axi_pdma memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_AXI_PDMA_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_AXI_PDMA_MEM_LP_MODE_M  (HP_SYSTEM_AXI_PDMA_MEM_LP_MODE_V << HP_SYSTEM_AXI_PDMA_MEM_LP_MODE_S)
#define HP_SYSTEM_AXI_PDMA_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_AXI_PDMA_MEM_LP_MODE_S  0
/** HP_SYSTEM_AXI_PDMA_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
 *  Set this bit to power down axi_pdma memory.
 */
#define HP_SYSTEM_AXI_PDMA_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_AXI_PDMA_MEM_LP_EN_M  (HP_SYSTEM_AXI_PDMA_MEM_LP_EN_V << HP_SYSTEM_AXI_PDMA_MEM_LP_EN_S)
#define HP_SYSTEM_AXI_PDMA_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_AXI_PDMA_MEM_LP_EN_S  2
/** HP_SYSTEM_AXI_PDMA_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control axi_pdma memory, disable hardware control.
 */
#define HP_SYSTEM_AXI_PDMA_MEM_LP_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_AXI_PDMA_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_AXI_PDMA_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_AXI_PDMA_MEM_LP_FORCE_CTRL_S)
#define HP_SYSTEM_AXI_PDMA_MEM_LP_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_AXI_PDMA_MEM_LP_FORCE_CTRL_S  3

/** HP_SYSTEM_ECC_MEM_LP_CTRL_REG register
 *  HP CORE0 & HP CORE1 memory power control register
 */
#define HP_SYSTEM_ECC_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x218)
/** HP_SYSTEM_ECC_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures ecc memory low power mode in low power stage.
 *  0: deep sleep
 *  1: light sleep
 *  2(default): shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_ECC_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_ECC_MEM_LP_MODE_M  (HP_SYSTEM_ECC_MEM_LP_MODE_V << HP_SYSTEM_ECC_MEM_LP_MODE_S)
#define HP_SYSTEM_ECC_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_ECC_MEM_LP_MODE_S  0
/** HP_SYSTEM_ECC_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
 *  Set this bit to power down ecc memory.
 */
#define HP_SYSTEM_ECC_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_ECC_MEM_LP_EN_M  (HP_SYSTEM_ECC_MEM_LP_EN_V << HP_SYSTEM_ECC_MEM_LP_EN_S)
#define HP_SYSTEM_ECC_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_ECC_MEM_LP_EN_S  2
/** HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control ecc memory, disable hardware control.
 */
#define HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL_S)
#define HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL_S  3

/** HP_SYSTEM_RSA_MEM_LP_CTRL_REG register
 *  HP CORE0 & HP CORE1 memory power control register
 */
#define HP_SYSTEM_RSA_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x21c)
/** HP_SYSTEM_RSA_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures rsa memory low power mode in low power stage.
 *  0: deep sleep
 *  1: light sleep
 *  2(default): shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_RSA_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_RSA_MEM_LP_MODE_M  (HP_SYSTEM_RSA_MEM_LP_MODE_V << HP_SYSTEM_RSA_MEM_LP_MODE_S)
#define HP_SYSTEM_RSA_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_RSA_MEM_LP_MODE_S  0
/** HP_SYSTEM_RSA_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
 *  Set this bit to power down rsa memory.
 */
#define HP_SYSTEM_RSA_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_RSA_MEM_LP_EN_M  (HP_SYSTEM_RSA_MEM_LP_EN_V << HP_SYSTEM_RSA_MEM_LP_EN_S)
#define HP_SYSTEM_RSA_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_RSA_MEM_LP_EN_S  2
/** HP_SYSTEM_RSA_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control rsa memory, disable hardware control.
 */
#define HP_SYSTEM_RSA_MEM_LP_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_RSA_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_RSA_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_RSA_MEM_LP_FORCE_CTRL_S)
#define HP_SYSTEM_RSA_MEM_LP_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_RSA_MEM_LP_FORCE_CTRL_S  3

/** HP_SYSTEM_BITSCRAM_MEM_LP_CTRL_REG register
 *  HP CORE0 & HP CORE1 memory power control register
 */
#define HP_SYSTEM_BITSCRAM_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x220)
/** HP_SYSTEM_BITSCRAM_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures bitscram memory low power mode in low power stage.
 *  0: deep sleep
 *  1: light sleep
 *  2(default): shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_BITSCRAM_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_BITSCRAM_MEM_LP_MODE_M  (HP_SYSTEM_BITSCRAM_MEM_LP_MODE_V << HP_SYSTEM_BITSCRAM_MEM_LP_MODE_S)
#define HP_SYSTEM_BITSCRAM_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_BITSCRAM_MEM_LP_MODE_S  0
/** HP_SYSTEM_BITSCRAM_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit to power down bitscram memory.
 */
#define HP_SYSTEM_BITSCRAM_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_BITSCRAM_MEM_LP_EN_M  (HP_SYSTEM_BITSCRAM_MEM_LP_EN_V << HP_SYSTEM_BITSCRAM_MEM_LP_EN_S)
#define HP_SYSTEM_BITSCRAM_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_BITSCRAM_MEM_LP_EN_S  2
/** HP_SYSTEM_BITSCRAM_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control bitscram memory, disable hardware control.
 */
#define HP_SYSTEM_BITSCRAM_MEM_LP_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_BITSCRAM_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_BITSCRAM_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_BITSCRAM_MEM_LP_FORCE_CTRL_S)
#define HP_SYSTEM_BITSCRAM_MEM_LP_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_BITSCRAM_MEM_LP_FORCE_CTRL_S  3

/** HP_SYSTEM_CAN0_MEM_LP_CTRL_REG register
 *  HP CORE0 & HP CORE1 memory power control register
 */
#define HP_SYSTEM_CAN0_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x228)
/** HP_SYSTEM_CAN0_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures can0 memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_CAN0_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_CAN0_MEM_LP_MODE_M  (HP_SYSTEM_CAN0_MEM_LP_MODE_V << HP_SYSTEM_CAN0_MEM_LP_MODE_S)
#define HP_SYSTEM_CAN0_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_CAN0_MEM_LP_MODE_S  0
/** HP_SYSTEM_CAN0_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit to power down can0 memory.
 */
#define HP_SYSTEM_CAN0_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_CAN0_MEM_LP_EN_M  (HP_SYSTEM_CAN0_MEM_LP_EN_V << HP_SYSTEM_CAN0_MEM_LP_EN_S)
#define HP_SYSTEM_CAN0_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_CAN0_MEM_LP_EN_S  2
/** HP_SYSTEM_CAN0_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control can0 memory, disable hardware control.
 */
#define HP_SYSTEM_CAN0_MEM_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_CAN0_MEM_FORCE_CTRL_M  (HP_SYSTEM_CAN0_MEM_FORCE_CTRL_V << HP_SYSTEM_CAN0_MEM_FORCE_CTRL_S)
#define HP_SYSTEM_CAN0_MEM_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_CAN0_MEM_FORCE_CTRL_S  3

/** HP_SYSTEM_MSPI_MEM_LP_CTRL_REG register
 *  HP CORE0 & HP CORE1 memory power control register
 */
#define HP_SYSTEM_MSPI_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x234)
/** HP_SYSTEM_PSRAM_MSPI_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures psram_mspi memory low power mode in low power stage.
 *  0: deep sleep
 *  1: light sleep
 *  2(default): shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_MODE_M  (HP_SYSTEM_PSRAM_MSPI_MEM_LP_MODE_V << HP_SYSTEM_PSRAM_MSPI_MEM_LP_MODE_S)
#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_MODE_S  0
/** HP_SYSTEM_PSRAM_MSPI_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
 *  Set this bit to power down psram_mspi memory.
 */
#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_EN_M  (HP_SYSTEM_PSRAM_MSPI_MEM_LP_EN_V << HP_SYSTEM_PSRAM_MSPI_MEM_LP_EN_S)
#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_EN_S  2
/** HP_SYSTEM_PSRAM_MSPI_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control psram_mspi memory, disable hardware control.
 */
#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_PSRAM_MSPI_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_PSRAM_MSPI_MEM_LP_FORCE_CTRL_S)
#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_FORCE_CTRL_S  3
/** HP_SYSTEM_FLASH_MSPI_MEM_LP_MODE : R/W; bitpos: [5:4]; default: 2;
 *  Configures flash_mspi memory low power mode in low power stage.
 *  0: deep sleep
 *  1: light sleep
 *  2(default): shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_FLASH_MSPI_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_FLASH_MSPI_MEM_LP_MODE_M  (HP_SYSTEM_FLASH_MSPI_MEM_LP_MODE_V << HP_SYSTEM_FLASH_MSPI_MEM_LP_MODE_S)
#define HP_SYSTEM_FLASH_MSPI_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_FLASH_MSPI_MEM_LP_MODE_S  4
/** HP_SYSTEM_FLASH_MSPI_MEM_LP_EN : R/W; bitpos: [6]; default: 0;
 *  Set this bit to power down flash_mspi memory.
 */
#define HP_SYSTEM_FLASH_MSPI_MEM_LP_EN    (BIT(6))
#define HP_SYSTEM_FLASH_MSPI_MEM_LP_EN_M  (HP_SYSTEM_FLASH_MSPI_MEM_LP_EN_V << HP_SYSTEM_FLASH_MSPI_MEM_LP_EN_S)
#define HP_SYSTEM_FLASH_MSPI_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_FLASH_MSPI_MEM_LP_EN_S  6
/** HP_SYSTEM_FLASH_MSPI_MEM_LP_FORCE_CTRL : R/W; bitpos: [7]; default: 0;
 *  Set this bit to force software control flash_mspi memory, disable hardware control.
 */
#define HP_SYSTEM_FLASH_MSPI_MEM_LP_FORCE_CTRL    (BIT(7))
#define HP_SYSTEM_FLASH_MSPI_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_FLASH_MSPI_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_FLASH_MSPI_MEM_LP_FORCE_CTRL_S)
#define HP_SYSTEM_FLASH_MSPI_MEM_LP_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_FLASH_MSPI_MEM_LP_FORCE_CTRL_S  7

/** HP_SYSTEM_HPCORE_MEM_LP_CTRL_REG register
 *  HP CORE0 & HP CORE1 memory power control register
 */
#define HP_SYSTEM_HPCORE_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x24c)
/** HP_SYSTEM_HPCORE_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
 *  Configures hpcore memory low power mode in low power stage.
 *  0: deep sleep
 *  1: light sleep
 *  2(default): shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_HPCORE_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_HPCORE_MEM_LP_MODE_M  (HP_SYSTEM_HPCORE_MEM_LP_MODE_V << HP_SYSTEM_HPCORE_MEM_LP_MODE_S)
#define HP_SYSTEM_HPCORE_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_HPCORE_MEM_LP_MODE_S  0
/** HP_SYSTEM_HPCORE_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
 *  Set this bit to power down hpcore memory.
 */
#define HP_SYSTEM_HPCORE_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_HPCORE_MEM_LP_EN_M  (HP_SYSTEM_HPCORE_MEM_LP_EN_V << HP_SYSTEM_HPCORE_MEM_LP_EN_S)
#define HP_SYSTEM_HPCORE_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_HPCORE_MEM_LP_EN_S  2
/** HP_SYSTEM_HPCORE_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control hpcore memory, disable hardware control.
 */
#define HP_SYSTEM_HPCORE_MEM_LP_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_HPCORE_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_HPCORE_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_HPCORE_MEM_LP_FORCE_CTRL_S)
#define HP_SYSTEM_HPCORE_MEM_LP_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_HPCORE_MEM_LP_FORCE_CTRL_S  3

/** HP_SYSTEM_ROM_MEM_LP_CTRL_REG register
 *  rom power control register
 */
#define HP_SYSTEM_ROM_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x250)
/** HP_SYSTEM_ROM_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures rom low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_ROM_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_ROM_MEM_LP_MODE_M  (HP_SYSTEM_ROM_MEM_LP_MODE_V << HP_SYSTEM_ROM_MEM_LP_MODE_S)
#define HP_SYSTEM_ROM_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_ROM_MEM_LP_MODE_S  0
/** HP_SYSTEM_ROM_MEM_LP_EN : R/W; bitpos: [3:2]; default: 0;
 *  Set this bit to power down rom.
 */
#define HP_SYSTEM_ROM_MEM_LP_EN    0x00000003U
#define HP_SYSTEM_ROM_MEM_LP_EN_M  (HP_SYSTEM_ROM_MEM_LP_EN_V << HP_SYSTEM_ROM_MEM_LP_EN_S)
#define HP_SYSTEM_ROM_MEM_LP_EN_V  0x00000003U
#define HP_SYSTEM_ROM_MEM_LP_EN_S  2
/** HP_SYSTEM_ROM_MEM_LP_FORCE_CTRL : R/W; bitpos: [5:4]; default: 0;
 *  Set this bit to force software control rom, disable hardware control.
 */
#define HP_SYSTEM_ROM_MEM_LP_FORCE_CTRL    0x00000003U
#define HP_SYSTEM_ROM_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_ROM_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_ROM_MEM_LP_FORCE_CTRL_S)
#define HP_SYSTEM_ROM_MEM_LP_FORCE_CTRL_V  0x00000003U
#define HP_SYSTEM_ROM_MEM_LP_FORCE_CTRL_S  4

/** HP_SYSTEM_L1_CACHE_MEM_LP_CTRL_REG register
 *  HP CORE0 & HP CORE1 memory power control register
 */
#define HP_SYSTEM_L1_CACHE_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x25c)
/** HP_SYSTEM_L1_CACHE_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures l1_cache memory low power mode in low power stage.
 *  0: deep sleep
 *  1: light sleep
 *  2(default): shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_L1_CACHE_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_L1_CACHE_MEM_LP_MODE_M  (HP_SYSTEM_L1_CACHE_MEM_LP_MODE_V << HP_SYSTEM_L1_CACHE_MEM_LP_MODE_S)
#define HP_SYSTEM_L1_CACHE_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_L1_CACHE_MEM_LP_MODE_S  0
/** HP_SYSTEM_L1_CACHE_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
 *  Set this bit to power down l1_cache memory.
 */
#define HP_SYSTEM_L1_CACHE_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_L1_CACHE_MEM_LP_EN_M  (HP_SYSTEM_L1_CACHE_MEM_LP_EN_V << HP_SYSTEM_L1_CACHE_MEM_LP_EN_S)
#define HP_SYSTEM_L1_CACHE_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_L1_CACHE_MEM_LP_EN_S  2
/** HP_SYSTEM_L1_CACHE_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control l1_cache memory, disable hardware control.
 */
#define HP_SYSTEM_L1_CACHE_MEM_LP_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_L1_CACHE_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_L1_CACHE_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_L1_CACHE_MEM_LP_FORCE_CTRL_S)
#define HP_SYSTEM_L1_CACHE_MEM_LP_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_L1_CACHE_MEM_LP_FORCE_CTRL_S  3

/** HP_SYSTEM_KYBER_MEM_LP_CTRL_REG register
 *  HP CORE0 & HP CORE1 memory power control register
 */
#define HP_SYSTEM_KYBER_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x260)
/** HP_SYSTEM_KYBER_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures kyber memory low power mode in low power stage.
 *  0: deep sleep
 *  1: light sleep
 *  2(default): shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_KYBER_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_KYBER_MEM_LP_MODE_M  (HP_SYSTEM_KYBER_MEM_LP_MODE_V << HP_SYSTEM_KYBER_MEM_LP_MODE_S)
#define HP_SYSTEM_KYBER_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_KYBER_MEM_LP_MODE_S  0
/** HP_SYSTEM_KYBER_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit to power down kyber memory.
 */
#define HP_SYSTEM_KYBER_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_KYBER_MEM_LP_EN_M  (HP_SYSTEM_KYBER_MEM_LP_EN_V << HP_SYSTEM_KYBER_MEM_LP_EN_S)
#define HP_SYSTEM_KYBER_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_KYBER_MEM_LP_EN_S  2
/** HP_SYSTEM_KYBER_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control kyber memory, disable hardware control.
 */
#define HP_SYSTEM_KYBER_MEM_LP_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_KYBER_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_KYBER_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_KYBER_MEM_LP_FORCE_CTRL_S)
#define HP_SYSTEM_KYBER_MEM_LP_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_KYBER_MEM_LP_FORCE_CTRL_S  3

/** HP_SYSTEM_LCDCAM_MEM_LP_CTRL_REG register
 *  HP CORE0 & HP CORE1 memory power control register
 */
#define HP_SYSTEM_LCDCAM_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x264)
/** HP_SYSTEM_LCDCAM_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures lcdcam memory low power mode in low power stage.
 *  0: deep sleep
 *  1: light sleep
 *  2(default): shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_LCDCAM_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_LCDCAM_MEM_LP_MODE_M  (HP_SYSTEM_LCDCAM_MEM_LP_MODE_V << HP_SYSTEM_LCDCAM_MEM_LP_MODE_S)
#define HP_SYSTEM_LCDCAM_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_LCDCAM_MEM_LP_MODE_S  0
/** HP_SYSTEM_LCDCAM_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit to power down lcdcam memory.
 */
#define HP_SYSTEM_LCDCAM_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_LCDCAM_MEM_LP_EN_M  (HP_SYSTEM_LCDCAM_MEM_LP_EN_V << HP_SYSTEM_LCDCAM_MEM_LP_EN_S)
#define HP_SYSTEM_LCDCAM_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_LCDCAM_MEM_LP_EN_S  2
/** HP_SYSTEM_LCDCAM_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control lcdcam memory, disable hardware control.
 */
#define HP_SYSTEM_LCDCAM_MEM_LP_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_LCDCAM_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_LCDCAM_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_LCDCAM_MEM_LP_FORCE_CTRL_S)
#define HP_SYSTEM_LCDCAM_MEM_LP_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_LCDCAM_MEM_LP_FORCE_CTRL_S  3

/** HP_SYSTEM_CPU_PERI0_TIMEOUT_CONF_REG register
 *  CPU_PERI0_TIMEOUT configuration register
 */
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x268)
/** HP_SYSTEM_CPU_PERI0_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
 *  Configures the timeout threshold for bus access for accessing CPU peripheral0
 *  register in the number of clock cycles of the clock domain.
 */
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_THRES    0x0000FFFFU
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_THRES_M  (HP_SYSTEM_CPU_PERI0_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI0_TIMEOUT_THRES_S)
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_THRES_V  0x0000FFFFU
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_THRES_S  0
/** HP_SYSTEM_CPU_PERI0_TIMEOUT_INT_CLR : WT; bitpos: [16]; default: 0;
 *  Write 1 to clear timeout interrupt.
 */
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_INT_CLR    (BIT(16))
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CPU_PERI0_TIMEOUT_INT_CLR_V << HP_SYSTEM_CPU_PERI0_TIMEOUT_INT_CLR_S)
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_INT_CLR_V  0x00000001U
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_INT_CLR_S  16
/** HP_SYSTEM_CPU_PERI0_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
 *  Configures whether or not to enable timeout protection for accessing CPU
 *  peripheral0 registers.
 *  0: Disable
 *  1: Enable
 */
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_PROTECT_EN    (BIT(17))
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_CPU_PERI0_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI0_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_PROTECT_EN_V  0x00000001U
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_PROTECT_EN_S  17

/** HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR_REG register
 *  CPU_PERI0_TIMEOUT_ADDR register
 */
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x26c)
/** HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
 *  Represents the address information of abnormal access.
 */
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR    0xFFFFFFFFU
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR_M  (HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR_S)
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR_V  0xFFFFFFFFU
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR_S  0

/** HP_SYSTEM_CPU_PERI0_TIMEOUT_UID_REG register
 *  CPU_PERI0_TIMEOUT_UID register
 */
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x270)
/** HP_SYSTEM_CPU_PERI0_TIMEOUT_UID : RO; bitpos: [7:0]; default: 0;
 *  Represents the master id[5:0] and master permission[6:5] when trigger timeout. This
 *  register will be cleared after the interrupt is cleared.
 */
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_UID    0x000000FFU
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_UID_M  (HP_SYSTEM_CPU_PERI0_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI0_TIMEOUT_UID_S)
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_UID_V  0x000000FFU
#define HP_SYSTEM_CPU_PERI0_TIMEOUT_UID_S  0

/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_CONF_REG register
 *  HP_SYSTEM_PERI0_TIMEOUT configuration register
 */
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x274)
/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
 *  Configures the timeout threshold for bus access for accessing CPU peripheral
 *  register in the number of clock cycles of the clock domain.
 */
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_THRES    0x0000FFFFU
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_THRES_M  (HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_THRES_V << HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_THRES_S)
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_THRES_V  0x0000FFFFU
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_THRES_S  0
/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_INT_CLR : WT; bitpos: [16]; default: 0;
 *  Write 1 to clear timeout interrupt.
 */
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_INT_CLR    (BIT(16))
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_INT_CLR_M  (HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_INT_CLR_V << HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_INT_CLR_S)
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_INT_CLR_V  0x00000001U
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_INT_CLR_S  16
/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
 *  Configures whether or not to enable timeout protection for accessing CPU peripheral
 *  registers.
 *  0: Disable
 *  1: Enable
 */
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_PROTECT_EN    (BIT(17))
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_PROTECT_EN_V  0x00000001U
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_PROTECT_EN_S  17

/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR_REG register
 *  HP_SYSTEM_PERI0_TIMEOUT_ADDR register
 */
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x278)
/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
 *  Represents the address information of abnormal access.
 */
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR    0xFFFFFFFFU
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR_M  (HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR_V << HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR_S)
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR_V  0xFFFFFFFFU
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR_S  0

/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID_REG register
 *  HP_SYSTEM_PERI0_TIMEOUT_UID register
 */
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x27c)
/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID : RO; bitpos: [7:0]; default: 0;
 *  Represents the master id[5:0] and master permission[6:5] when trigger timeout. This
 *  register will be cleared after the interrupt is cleared.
 */
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID    0x000000FFU
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID_M  (HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID_V << HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID_S)
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID_V  0x000000FFU
#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID_S  0

/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_CONF_REG register
 *  HP_SYSTEM_PERI1_TIMEOUT configuration register
 */
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x280)
/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
 *  Configures the timeout threshold for bus access for accessing CPU peripheral
 *  register in the number of clock cycles of the clock domain.
 */
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_THRES    0x0000FFFFU
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_THRES_M  (HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_THRES_V << HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_THRES_S)
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_THRES_V  0x0000FFFFU
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_THRES_S  0
/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_INT_CLR : WT; bitpos: [16]; default: 0;
 *  Write 1 to clear timeout interrupt.
 */
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_INT_CLR    (BIT(16))
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_INT_CLR_M  (HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_INT_CLR_V << HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_INT_CLR_S)
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_INT_CLR_V  0x00000001U
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_INT_CLR_S  16
/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
 *  Configures whether or not to enable timeout protection for accessing CPU peripheral
 *  registers.
 *  0: Disable
 *  1: Enable
 */
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_PROTECT_EN    (BIT(17))
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_PROTECT_EN_V  0x00000001U
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_PROTECT_EN_S  17

/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR_REG register
 *  HP_SYSTEM_PERI1_TIMEOUT_ADDR register
 */
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x284)
/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
 *  Represents the address information of abnormal access.
 */
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR    0xFFFFFFFFU
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR_M  (HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR_V << HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR_S)
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR_V  0xFFFFFFFFU
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR_S  0

/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID_REG register
 *  HP_SYSTEM_PERI1_TIMEOUT_UID register
 */
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x288)
/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID : RO; bitpos: [7:0]; default: 0;
 *  Represents the master id[5:0] and master permission[6:5] when trigger timeout. This
 *  register will be cleared after the interrupt is cleared.
 */
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID    0x000000FFU
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID_M  (HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID_V << HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID_S)
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID_V  0x000000FFU
#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID_S  0

/** HP_SYSTEM_UART0_MEM_LP_CTRL_REG register
 *  uart memory power control register
 */
#define HP_SYSTEM_UART0_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x28c)
/** HP_SYSTEM_UART0_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
 *  Configures uart0 memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_UART0_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_UART0_MEM_LP_MODE_M  (HP_SYSTEM_UART0_MEM_LP_MODE_V << HP_SYSTEM_UART0_MEM_LP_MODE_S)
#define HP_SYSTEM_UART0_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_UART0_MEM_LP_MODE_S  0
/** HP_SYSTEM_UART0_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
 *  Set this bit to power down uart0 memory.
 */
#define HP_SYSTEM_UART0_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_UART0_MEM_LP_EN_M  (HP_SYSTEM_UART0_MEM_LP_EN_V << HP_SYSTEM_UART0_MEM_LP_EN_S)
#define HP_SYSTEM_UART0_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_UART0_MEM_LP_EN_S  2
/** HP_SYSTEM_UART0_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control uart0 memory, disable hardware control.
 */
#define HP_SYSTEM_UART0_MEM_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_UART0_MEM_FORCE_CTRL_M  (HP_SYSTEM_UART0_MEM_FORCE_CTRL_V << HP_SYSTEM_UART0_MEM_FORCE_CTRL_S)
#define HP_SYSTEM_UART0_MEM_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_UART0_MEM_FORCE_CTRL_S  3

/** HP_SYSTEM_UART1_MEM_LP_CTRL_REG register
 *  uart memory power control register
 */
#define HP_SYSTEM_UART1_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x290)
/** HP_SYSTEM_UART1_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures uart1 memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_UART1_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_UART1_MEM_LP_MODE_M  (HP_SYSTEM_UART1_MEM_LP_MODE_V << HP_SYSTEM_UART1_MEM_LP_MODE_S)
#define HP_SYSTEM_UART1_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_UART1_MEM_LP_MODE_S  0
/** HP_SYSTEM_UART1_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit to power down uart1 memory.
 */
#define HP_SYSTEM_UART1_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_UART1_MEM_LP_EN_M  (HP_SYSTEM_UART1_MEM_LP_EN_V << HP_SYSTEM_UART1_MEM_LP_EN_S)
#define HP_SYSTEM_UART1_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_UART1_MEM_LP_EN_S  2
/** HP_SYSTEM_UART1_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control uart1 memory, disable hardware control.
 */
#define HP_SYSTEM_UART1_MEM_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_UART1_MEM_FORCE_CTRL_M  (HP_SYSTEM_UART1_MEM_FORCE_CTRL_V << HP_SYSTEM_UART1_MEM_FORCE_CTRL_S)
#define HP_SYSTEM_UART1_MEM_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_UART1_MEM_FORCE_CTRL_S  3

/** HP_SYSTEM_UART2_MEM_LP_CTRL_REG register
 *  uart memory power control register
 */
#define HP_SYSTEM_UART2_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x294)
/** HP_SYSTEM_UART2_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures uart2 memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_UART2_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_UART2_MEM_LP_MODE_M  (HP_SYSTEM_UART2_MEM_LP_MODE_V << HP_SYSTEM_UART2_MEM_LP_MODE_S)
#define HP_SYSTEM_UART2_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_UART2_MEM_LP_MODE_S  0
/** HP_SYSTEM_UART2_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit to power down uart2 memory.
 */
#define HP_SYSTEM_UART2_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_UART2_MEM_LP_EN_M  (HP_SYSTEM_UART2_MEM_LP_EN_V << HP_SYSTEM_UART2_MEM_LP_EN_S)
#define HP_SYSTEM_UART2_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_UART2_MEM_LP_EN_S  2
/** HP_SYSTEM_UART2_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control uart2 memory, disable hardware control.
 */
#define HP_SYSTEM_UART2_MEM_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_UART2_MEM_FORCE_CTRL_M  (HP_SYSTEM_UART2_MEM_FORCE_CTRL_V << HP_SYSTEM_UART2_MEM_FORCE_CTRL_S)
#define HP_SYSTEM_UART2_MEM_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_UART2_MEM_FORCE_CTRL_S  3

/** HP_SYSTEM_LEDC1_MEM_LP_CTRL_REG register
 *  ledc1 memory power control register
 */
#define HP_SYSTEM_LEDC1_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x298)
/** HP_SYSTEM_LEDC1_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures ledc1 memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_LEDC1_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_LEDC1_MEM_LP_MODE_M  (HP_SYSTEM_LEDC1_MEM_LP_MODE_V << HP_SYSTEM_LEDC1_MEM_LP_MODE_S)
#define HP_SYSTEM_LEDC1_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_LEDC1_MEM_LP_MODE_S  0
/** HP_SYSTEM_LEDC1_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit to power down ledc1 memory.
 */
#define HP_SYSTEM_LEDC1_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_LEDC1_MEM_LP_EN_M  (HP_SYSTEM_LEDC1_MEM_LP_EN_V << HP_SYSTEM_LEDC1_MEM_LP_EN_S)
#define HP_SYSTEM_LEDC1_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_LEDC1_MEM_LP_EN_S  2
/** HP_SYSTEM_LEDC1_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control ledc1 memory, disable hardware control.
 */
#define HP_SYSTEM_LEDC1_MEM_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_LEDC1_MEM_FORCE_CTRL_M  (HP_SYSTEM_LEDC1_MEM_FORCE_CTRL_V << HP_SYSTEM_LEDC1_MEM_FORCE_CTRL_S)
#define HP_SYSTEM_LEDC1_MEM_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_LEDC1_MEM_FORCE_CTRL_S  3

/** HP_SYSTEM_PPA_MEM_LP_CTRL_REG register
 *  vpu memory power control register
 */
#define HP_SYSTEM_PPA_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x29c)
/** HP_SYSTEM_PPA_SPRF_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures ppa_sprf memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_PPA_SPRF_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_PPA_SPRF_MEM_LP_MODE_M  (HP_SYSTEM_PPA_SPRF_MEM_LP_MODE_V << HP_SYSTEM_PPA_SPRF_MEM_LP_MODE_S)
#define HP_SYSTEM_PPA_SPRF_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_PPA_SPRF_MEM_LP_MODE_S  0
/** HP_SYSTEM_PPA_SPRF_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit to power down ppa_sprf memory.
 */
#define HP_SYSTEM_PPA_SPRF_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_PPA_SPRF_MEM_LP_EN_M  (HP_SYSTEM_PPA_SPRF_MEM_LP_EN_V << HP_SYSTEM_PPA_SPRF_MEM_LP_EN_S)
#define HP_SYSTEM_PPA_SPRF_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_PPA_SPRF_MEM_LP_EN_S  2
/** HP_SYSTEM_PPA_SPRF_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control ppa_sprf memory, disable hardware control.
 */
#define HP_SYSTEM_PPA_SPRF_MEM_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_PPA_SPRF_MEM_FORCE_CTRL_M  (HP_SYSTEM_PPA_SPRF_MEM_FORCE_CTRL_V << HP_SYSTEM_PPA_SPRF_MEM_FORCE_CTRL_S)
#define HP_SYSTEM_PPA_SPRF_MEM_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_PPA_SPRF_MEM_FORCE_CTRL_S  3

/** HP_SYSTEM_JPEG_MEM_LP_CTRL_REG register
 *  vpu memory power control register
 */
#define HP_SYSTEM_JPEG_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x2a0)
/** HP_SYSTEM_JPEG_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures jpeg memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_JPEG_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_JPEG_MEM_LP_MODE_M  (HP_SYSTEM_JPEG_MEM_LP_MODE_V << HP_SYSTEM_JPEG_MEM_LP_MODE_S)
#define HP_SYSTEM_JPEG_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_JPEG_MEM_LP_MODE_S  0
/** HP_SYSTEM_JPEG_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit to power down jpeg memory.
 */
#define HP_SYSTEM_JPEG_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_JPEG_MEM_LP_EN_M  (HP_SYSTEM_JPEG_MEM_LP_EN_V << HP_SYSTEM_JPEG_MEM_LP_EN_S)
#define HP_SYSTEM_JPEG_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_JPEG_MEM_LP_EN_S  2
/** HP_SYSTEM_JPEG_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control jpeg memory, disable hardware control.
 */
#define HP_SYSTEM_JPEG_MEM_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_JPEG_MEM_FORCE_CTRL_M  (HP_SYSTEM_JPEG_MEM_FORCE_CTRL_V << HP_SYSTEM_JPEG_MEM_FORCE_CTRL_S)
#define HP_SYSTEM_JPEG_MEM_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_JPEG_MEM_FORCE_CTRL_S  3

/** HP_SYSTEM_CAN1_MEM_LP_CTRL_REG register
 *  HP CORE0 & HP CORE1 memory power control register
 */
#define HP_SYSTEM_CAN1_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x2a4)
/** HP_SYSTEM_CAN1_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
 *  Configures can1 memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_SYSTEM_CAN1_MEM_LP_MODE    0x00000003U
#define HP_SYSTEM_CAN1_MEM_LP_MODE_M  (HP_SYSTEM_CAN1_MEM_LP_MODE_V << HP_SYSTEM_CAN1_MEM_LP_MODE_S)
#define HP_SYSTEM_CAN1_MEM_LP_MODE_V  0x00000003U
#define HP_SYSTEM_CAN1_MEM_LP_MODE_S  0
/** HP_SYSTEM_CAN1_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit to power down can1 memory.
 */
#define HP_SYSTEM_CAN1_MEM_LP_EN    (BIT(2))
#define HP_SYSTEM_CAN1_MEM_LP_EN_M  (HP_SYSTEM_CAN1_MEM_LP_EN_V << HP_SYSTEM_CAN1_MEM_LP_EN_S)
#define HP_SYSTEM_CAN1_MEM_LP_EN_V  0x00000001U
#define HP_SYSTEM_CAN1_MEM_LP_EN_S  2
/** HP_SYSTEM_CAN1_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control can1 memory, disable hardware control.
 */
#define HP_SYSTEM_CAN1_MEM_FORCE_CTRL    (BIT(3))
#define HP_SYSTEM_CAN1_MEM_FORCE_CTRL_M  (HP_SYSTEM_CAN1_MEM_FORCE_CTRL_V << HP_SYSTEM_CAN1_MEM_FORCE_CTRL_S)
#define HP_SYSTEM_CAN1_MEM_FORCE_CTRL_V  0x00000001U
#define HP_SYSTEM_CAN1_MEM_FORCE_CTRL_S  3

/** HP_SYSTEM_CPU_PERI1_TIMEOUT_CONF_REG register
 *  CPU_PERI1_TIMEOUT configuration register
 */
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x2a8)
/** HP_SYSTEM_CPU_PERI1_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
 *  Configures the timeout threshold for bus access for accessing CPU peripheral
 *  register in the number of clock cycles of the clock domain.
 */
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_THRES    0x0000FFFFU
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_THRES_M  (HP_SYSTEM_CPU_PERI1_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI1_TIMEOUT_THRES_S)
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_THRES_V  0x0000FFFFU
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_THRES_S  0
/** HP_SYSTEM_CPU_PERI1_TIMEOUT_INT_CLR : WT; bitpos: [16]; default: 0;
 *  Write 1 to clear timeout interrupt.
 */
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_INT_CLR    (BIT(16))
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CPU_PERI1_TIMEOUT_INT_CLR_V << HP_SYSTEM_CPU_PERI1_TIMEOUT_INT_CLR_S)
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_INT_CLR_V  0x00000001U
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_INT_CLR_S  16
/** HP_SYSTEM_CPU_PERI1_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
 *  Configures whether or not to enable timeout protection for accessing CPU
 *  peripheral11 registers.
 *  0: Disable
 *  1: Enable
 */
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_PROTECT_EN    (BIT(17))
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_CPU_PERI1_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI1_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_PROTECT_EN_V  0x00000001U
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_PROTECT_EN_S  17

/** HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR_REG register
 *  CPU_PERI1_TIMEOUT_ADDR register
 */
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x2ac)
/** HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
 *  Represents the address information of abnormal access.
 */
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR    0xFFFFFFFFU
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR_M  (HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR_S)
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR_V  0xFFFFFFFFU
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR_S  0

/** HP_SYSTEM_CPU_PERI1_TIMEOUT_UID_REG register
 *  CPU_PERI1_TIMEOUT_UID register
 */
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x2b0)
/** HP_SYSTEM_CPU_PERI1_TIMEOUT_UID : RO; bitpos: [7:0]; default: 0;
 *  Represents the master id[5:0] and master permission[6:5] when trigger timeout. This
 *  register will be cleared after the interrupt is cleared.
 */
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_UID    0x000000FFU
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_UID_M  (HP_SYSTEM_CPU_PERI1_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI1_TIMEOUT_UID_S)
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_UID_V  0x000000FFU
#define HP_SYSTEM_CPU_PERI1_TIMEOUT_UID_S  0

/** HP_SYSTEM_CPU_ACS_CACHE_MEM_CONF_REG register
 *  CPU access Cache data mem configuration register
 */
#define HP_SYSTEM_CPU_ACS_CACHE_MEM_CONF_REG (DR_REG_HP_SYS_BASE + 0x2b4)
/** HP_SYSTEM_CPU_ACCESS_AC0_DATAMEM_EN : HRO; bitpos: [0]; default: 0;
 *  Set this bit to enable CPU accessROMCache0 data mem path
 */
#define HP_SYSTEM_CPU_ACCESS_AC0_DATAMEM_EN    (BIT(0))
#define HP_SYSTEM_CPU_ACCESS_AC0_DATAMEM_EN_M  (HP_SYSTEM_CPU_ACCESS_AC0_DATAMEM_EN_V << HP_SYSTEM_CPU_ACCESS_AC0_DATAMEM_EN_S)
#define HP_SYSTEM_CPU_ACCESS_AC0_DATAMEM_EN_V  0x00000001U
#define HP_SYSTEM_CPU_ACCESS_AC0_DATAMEM_EN_S  0
/** HP_SYSTEM_CPU_ACCESS_AC1_DATAMEM_EN : HRO; bitpos: [1]; default: 0;
 *  Set this bit to enable CPU access ROMCache1 data mem path
 */
#define HP_SYSTEM_CPU_ACCESS_AC1_DATAMEM_EN    (BIT(1))
#define HP_SYSTEM_CPU_ACCESS_AC1_DATAMEM_EN_M  (HP_SYSTEM_CPU_ACCESS_AC1_DATAMEM_EN_V << HP_SYSTEM_CPU_ACCESS_AC1_DATAMEM_EN_S)
#define HP_SYSTEM_CPU_ACCESS_AC1_DATAMEM_EN_V  0x00000001U
#define HP_SYSTEM_CPU_ACCESS_AC1_DATAMEM_EN_S  1
/** HP_SYSTEM_CPU_ACCESS_IC0_DATAMEM_EN : R/W; bitpos: [2]; default: 0;
 *  Set this bit to enable CPU access ICache0 data mem path
 */
#define HP_SYSTEM_CPU_ACCESS_IC0_DATAMEM_EN    (BIT(2))
#define HP_SYSTEM_CPU_ACCESS_IC0_DATAMEM_EN_M  (HP_SYSTEM_CPU_ACCESS_IC0_DATAMEM_EN_V << HP_SYSTEM_CPU_ACCESS_IC0_DATAMEM_EN_S)
#define HP_SYSTEM_CPU_ACCESS_IC0_DATAMEM_EN_V  0x00000001U
#define HP_SYSTEM_CPU_ACCESS_IC0_DATAMEM_EN_S  2
/** HP_SYSTEM_CPU_ACCESS_IC1_DATAMEM_EN : R/W; bitpos: [3]; default: 0;
 *  Set this bit to enable CPU access ICache1 data mem path
 */
#define HP_SYSTEM_CPU_ACCESS_IC1_DATAMEM_EN    (BIT(3))
#define HP_SYSTEM_CPU_ACCESS_IC1_DATAMEM_EN_M  (HP_SYSTEM_CPU_ACCESS_IC1_DATAMEM_EN_V << HP_SYSTEM_CPU_ACCESS_IC1_DATAMEM_EN_S)
#define HP_SYSTEM_CPU_ACCESS_IC1_DATAMEM_EN_V  0x00000001U
#define HP_SYSTEM_CPU_ACCESS_IC1_DATAMEM_EN_S  3
/** HP_SYSTEM_CPU_ACCESS_DC_DATAMEM_EN : R/W; bitpos: [4]; default: 0;
 *  Set this bit to enable CPU access DCache data mem path
 */
#define HP_SYSTEM_CPU_ACCESS_DC_DATAMEM_EN    (BIT(4))
#define HP_SYSTEM_CPU_ACCESS_DC_DATAMEM_EN_M  (HP_SYSTEM_CPU_ACCESS_DC_DATAMEM_EN_V << HP_SYSTEM_CPU_ACCESS_DC_DATAMEM_EN_S)
#define HP_SYSTEM_CPU_ACCESS_DC_DATAMEM_EN_V  0x00000001U
#define HP_SYSTEM_CPU_ACCESS_DC_DATAMEM_EN_S  4
/** HP_SYSTEM_CPU_ACS_CACHE_MEM_LOCK : R/W; bitpos: [5]; default: 0;
 *  Set 1 to lock cpu acs mem data mem path configuration
 */
#define HP_SYSTEM_CPU_ACS_CACHE_MEM_LOCK    (BIT(5))
#define HP_SYSTEM_CPU_ACS_CACHE_MEM_LOCK_M  (HP_SYSTEM_CPU_ACS_CACHE_MEM_LOCK_V << HP_SYSTEM_CPU_ACS_CACHE_MEM_LOCK_S)
#define HP_SYSTEM_CPU_ACS_CACHE_MEM_LOCK_V  0x00000001U
#define HP_SYSTEM_CPU_ACS_CACHE_MEM_LOCK_S  5

/** HP_SYSTEM_TCM_PERFORMACE_CTRL_REG register
 *  need_des
 */
#define HP_SYSTEM_TCM_PERFORMACE_CTRL_REG (DR_REG_HP_SYS_BASE + 0x2e0)
/** HP_SYSTEM_AHB_TO_TCM_MEM_EN_HOLD : R/W; bitpos: [0]; default: 0;
 *  Set 1 to keep TCM mem enable hold when mem access is busy.
 */
#define HP_SYSTEM_AHB_TO_TCM_MEM_EN_HOLD    (BIT(0))
#define HP_SYSTEM_AHB_TO_TCM_MEM_EN_HOLD_M  (HP_SYSTEM_AHB_TO_TCM_MEM_EN_HOLD_V << HP_SYSTEM_AHB_TO_TCM_MEM_EN_HOLD_S)
#define HP_SYSTEM_AHB_TO_TCM_MEM_EN_HOLD_V  0x00000001U
#define HP_SYSTEM_AHB_TO_TCM_MEM_EN_HOLD_S  0

/** HP_SYSTEM_SDIO_PAD_BIST_CFG_REG register
 *  sdio pad bist control register
 */
#define HP_SYSTEM_SDIO_PAD_BIST_CFG_REG (DR_REG_HP_SYS_BASE + 0x2e4)
/** HP_SYSTEM_SDIO_PAD_BIST_START : WT; bitpos: [0]; default: 0;
 *  Write 1 to start sdio pad bist
 */
#define HP_SYSTEM_SDIO_PAD_BIST_START    (BIT(0))
#define HP_SYSTEM_SDIO_PAD_BIST_START_M  (HP_SYSTEM_SDIO_PAD_BIST_START_V << HP_SYSTEM_SDIO_PAD_BIST_START_S)
#define HP_SYSTEM_SDIO_PAD_BIST_START_V  0x00000001U
#define HP_SYSTEM_SDIO_PAD_BIST_START_S  0

/** HP_SYSTEM_SDIO_PAD_BIST_INT_RAW_REG register
 *  sdio pad bist interrupt raw register
 */
#define HP_SYSTEM_SDIO_PAD_BIST_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x2e8)
/** HP_SYSTEM_SDIO_PAD_BIST_OK_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
 *  intr triggered when bist finish and status is bist ok
 */
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_RAW    (BIT(0))
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_RAW_M  (HP_SYSTEM_SDIO_PAD_BIST_OK_INT_RAW_V << HP_SYSTEM_SDIO_PAD_BIST_OK_INT_RAW_S)
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_RAW_V  0x00000001U
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_RAW_S  0
/** HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
 *  intr triggered when bist finish and status is bist fail
 */
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_RAW    (BIT(1))
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_RAW_M  (HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_RAW_V << HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_RAW_S)
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_RAW_V  0x00000001U
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_RAW_S  1

/** HP_SYSTEM_SDIO_PAD_BIST_INT_ST_REG register
 *  masked interrupt register
 */
#define HP_SYSTEM_SDIO_PAD_BIST_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x2ec)
/** HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ST : RO; bitpos: [0]; default: 0;
 *  the masked interrupt status of sdio pad bist ok interrupt
 */
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ST    (BIT(0))
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ST_M  (HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ST_V << HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ST_S)
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ST_V  0x00000001U
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ST_S  0
/** HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ST : RO; bitpos: [1]; default: 0;
 *  the masked interrupt status of sdio pad bist fail interrupt
 */
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ST    (BIT(1))
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ST_M  (HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ST_V << HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ST_S)
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ST_V  0x00000001U
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ST_S  1

/** HP_SYSTEM_SDIO_PAD_BIST_INT_ENA_REG register
 *  interrupt enable register
 */
#define HP_SYSTEM_SDIO_PAD_BIST_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x2f0)
/** HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ENA : R/W; bitpos: [0]; default: 0;
 *  Write 1 to enable sdio pad bist ok interrupt
 */
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ENA    (BIT(0))
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ENA_M  (HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ENA_V << HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ENA_S)
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ENA_V  0x00000001U
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ENA_S  0
/** HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ENA : R/W; bitpos: [1]; default: 0;
 *  Write 1 to enable sdio pad bist fail interrupt
 */
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ENA    (BIT(1))
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ENA_M  (HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ENA_V << HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ENA_S)
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ENA_V  0x00000001U
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ENA_S  1

/** HP_SYSTEM_SDIO_PAD_BIST_INT_CLR_REG register
 *  interrupt clear register
 */
#define HP_SYSTEM_SDIO_PAD_BIST_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x2f4)
/** HP_SYSTEM_SDIO_PAD_BIST_OK_INT_CLR : WT; bitpos: [0]; default: 0;
 *  Write 1 to clr sdio pad bist ok interrupt
 */
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_CLR    (BIT(0))
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_CLR_M  (HP_SYSTEM_SDIO_PAD_BIST_OK_INT_CLR_V << HP_SYSTEM_SDIO_PAD_BIST_OK_INT_CLR_S)
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_CLR_V  0x00000001U
#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_CLR_S  0
/** HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_CLR : WT; bitpos: [1]; default: 0;
 *  Write 1 to clr sdio pad bist fail interrupt
 */
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_CLR    (BIT(1))
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_CLR_M  (HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_CLR_V << HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_CLR_S)
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_CLR_V  0x00000001U
#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_CLR_S  1

/** HP_SYSTEM_SDIO_PAD_BIST_ST_REG register
 *  sdio pad bist status register
 */
#define HP_SYSTEM_SDIO_PAD_BIST_ST_REG (DR_REG_HP_SYS_BASE + 0x2f8)
/** HP_SYSTEM_SDIO_PAD_BIST_RCNT : RO; bitpos: [5:0]; default: 0;
 *  Indicate number of clock cycles received for pad bist debug
 */
#define HP_SYSTEM_SDIO_PAD_BIST_RCNT    0x0000003FU
#define HP_SYSTEM_SDIO_PAD_BIST_RCNT_M  (HP_SYSTEM_SDIO_PAD_BIST_RCNT_V << HP_SYSTEM_SDIO_PAD_BIST_RCNT_S)
#define HP_SYSTEM_SDIO_PAD_BIST_RCNT_V  0x0000003FU
#define HP_SYSTEM_SDIO_PAD_BIST_RCNT_S  0

/** HP_SYSTEM_GMAC0_PAD_BIST_CFG_REG register
 *  gmac0 pad bist control register
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_CFG_REG (DR_REG_HP_SYS_BASE + 0x2fc)
/** HP_SYSTEM_GMAC0_PAD_BIST_START : WT; bitpos: [0]; default: 0;
 *  Write 1 to start gmac0 pad bist
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_START    (BIT(0))
#define HP_SYSTEM_GMAC0_PAD_BIST_START_M  (HP_SYSTEM_GMAC0_PAD_BIST_START_V << HP_SYSTEM_GMAC0_PAD_BIST_START_S)
#define HP_SYSTEM_GMAC0_PAD_BIST_START_V  0x00000001U
#define HP_SYSTEM_GMAC0_PAD_BIST_START_S  0

/** HP_SYSTEM_GMAC0_PAD_BIST_INT_RAW_REG register
 *  gmac0 pad bist interrupt raw register
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x300)
/** HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
 *  intr triggered when bist finish and status is bist ok
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_RAW    (BIT(0))
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_RAW_M  (HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_RAW_V << HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_RAW_S)
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_RAW_V  0x00000001U
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_RAW_S  0
/** HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
 *  intr triggered when bist finish and status is bist fail
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_RAW    (BIT(1))
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_RAW_M  (HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_RAW_V << HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_RAW_S)
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_RAW_V  0x00000001U
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_RAW_S  1

/** HP_SYSTEM_GMAC0_PAD_BIST_INT_ST_REG register
 *  masked interrupt register
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x304)
/** HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ST : RO; bitpos: [0]; default: 0;
 *  the masked interrupt status of gmac0 pad bist ok interrupt
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ST    (BIT(0))
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ST_M  (HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ST_V << HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ST_S)
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ST_V  0x00000001U
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ST_S  0
/** HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ST : RO; bitpos: [1]; default: 0;
 *  the masked interrupt status of gmac0 pad bist fail interrupt
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ST    (BIT(1))
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ST_M  (HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ST_V << HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ST_S)
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ST_V  0x00000001U
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ST_S  1

/** HP_SYSTEM_GMAC0_PAD_BIST_INT_ENA_REG register
 *  interrupt enable register
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x308)
/** HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ENA : R/W; bitpos: [0]; default: 0;
 *  Write 1 to enable gmac0 pad bist ok interrupt
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ENA    (BIT(0))
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ENA_M  (HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ENA_V << HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ENA_S)
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ENA_V  0x00000001U
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ENA_S  0
/** HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ENA : R/W; bitpos: [1]; default: 0;
 *  Write 1 to enable gmac0 pad bist fail interrupt
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ENA    (BIT(1))
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ENA_M  (HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ENA_V << HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ENA_S)
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ENA_V  0x00000001U
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ENA_S  1

/** HP_SYSTEM_GMAC0_PAD_BIST_INT_CLR_REG register
 *  interrupt clear register
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x30c)
/** HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_CLR : WT; bitpos: [0]; default: 0;
 *  Write 1 to clr gmac0 pad bist ok interrupt
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_CLR    (BIT(0))
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_CLR_M  (HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_CLR_V << HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_CLR_S)
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_CLR_V  0x00000001U
#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_CLR_S  0
/** HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_CLR : WT; bitpos: [1]; default: 0;
 *  Write 1 to clr gmac0 pad bist fail interrupt
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_CLR    (BIT(1))
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_CLR_M  (HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_CLR_V << HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_CLR_S)
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_CLR_V  0x00000001U
#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_CLR_S  1

/** HP_SYSTEM_GMAC0_PAD_BIST_ST_REG register
 *  gmac0 pad bist status register
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_ST_REG (DR_REG_HP_SYS_BASE + 0x310)
/** HP_SYSTEM_GMAC0_PAD_BIST_RCNT : RO; bitpos: [5:0]; default: 0;
 *  Indicate number of clock cycles received for pad bist debug
 */
#define HP_SYSTEM_GMAC0_PAD_BIST_RCNT    0x0000003FU
#define HP_SYSTEM_GMAC0_PAD_BIST_RCNT_M  (HP_SYSTEM_GMAC0_PAD_BIST_RCNT_V << HP_SYSTEM_GMAC0_PAD_BIST_RCNT_S)
#define HP_SYSTEM_GMAC0_PAD_BIST_RCNT_V  0x0000003FU
#define HP_SYSTEM_GMAC0_PAD_BIST_RCNT_S  0

/** HP_SYSTEM_GMAC1_PAD_BIST_CFG_REG register
 *  gmac1 pad bist control register
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_CFG_REG (DR_REG_HP_SYS_BASE + 0x314)
/** HP_SYSTEM_GMAC1_PAD_BIST_START : WT; bitpos: [0]; default: 0;
 *  Write 1 to start gmac1 pad bist
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_START    (BIT(0))
#define HP_SYSTEM_GMAC1_PAD_BIST_START_M  (HP_SYSTEM_GMAC1_PAD_BIST_START_V << HP_SYSTEM_GMAC1_PAD_BIST_START_S)
#define HP_SYSTEM_GMAC1_PAD_BIST_START_V  0x00000001U
#define HP_SYSTEM_GMAC1_PAD_BIST_START_S  0

/** HP_SYSTEM_GMAC1_PAD_BIST_INT_RAW_REG register
 *  gmac1 pad bist interrupt raw register
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x318)
/** HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
 *  intr triggered when bist finish and status is bist ok
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_RAW    (BIT(0))
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_RAW_M  (HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_RAW_V << HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_RAW_S)
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_RAW_V  0x00000001U
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_RAW_S  0
/** HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
 *  intr triggered when bist finish and status is bist fail
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_RAW    (BIT(1))
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_RAW_M  (HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_RAW_V << HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_RAW_S)
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_RAW_V  0x00000001U
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_RAW_S  1

/** HP_SYSTEM_GMAC1_PAD_BIST_INT_ST_REG register
 *  masked interrupt register
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x31c)
/** HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ST : RO; bitpos: [0]; default: 0;
 *  the masked interrupt status of gmac1 pad bist ok interrupt
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ST    (BIT(0))
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ST_M  (HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ST_V << HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ST_S)
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ST_V  0x00000001U
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ST_S  0
/** HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ST : RO; bitpos: [1]; default: 0;
 *  the masked interrupt status of gmac1 pad bist fail interrupt
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ST    (BIT(1))
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ST_M  (HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ST_V << HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ST_S)
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ST_V  0x00000001U
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ST_S  1

/** HP_SYSTEM_GMAC1_PAD_BIST_INT_ENA_REG register
 *  interrupt enable register
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x320)
/** HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ENA : R/W; bitpos: [0]; default: 0;
 *  Write 1 to enable gmac1 pad bist ok interrupt
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ENA    (BIT(0))
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ENA_M  (HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ENA_V << HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ENA_S)
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ENA_V  0x00000001U
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ENA_S  0
/** HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ENA : R/W; bitpos: [1]; default: 0;
 *  Write 1 to enable gmac1 pad bist fail interrupt
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ENA    (BIT(1))
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ENA_M  (HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ENA_V << HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ENA_S)
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ENA_V  0x00000001U
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ENA_S  1

/** HP_SYSTEM_GMAC1_PAD_BIST_INT_CLR_REG register
 *  interrupt clear register
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x324)
/** HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_CLR : WT; bitpos: [0]; default: 0;
 *  Write 1 to clr gmac1 pad bist ok interrupt
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_CLR    (BIT(0))
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_CLR_M  (HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_CLR_V << HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_CLR_S)
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_CLR_V  0x00000001U
#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_CLR_S  0
/** HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_CLR : WT; bitpos: [1]; default: 0;
 *  Write 1 to clr gmac1 pad bist fail interrupt
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_CLR    (BIT(1))
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_CLR_M  (HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_CLR_V << HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_CLR_S)
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_CLR_V  0x00000001U
#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_CLR_S  1

/** HP_SYSTEM_GMAC1_PAD_BIST_ST_REG register
 *  gmac1 pad bist status register
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_ST_REG (DR_REG_HP_SYS_BASE + 0x328)
/** HP_SYSTEM_GMAC1_PAD_BIST_RCNT : RO; bitpos: [5:0]; default: 0;
 *  Indicate number of clock cycles received for pad bist debug
 */
#define HP_SYSTEM_GMAC1_PAD_BIST_RCNT    0x0000003FU
#define HP_SYSTEM_GMAC1_PAD_BIST_RCNT_M  (HP_SYSTEM_GMAC1_PAD_BIST_RCNT_V << HP_SYSTEM_GMAC1_PAD_BIST_RCNT_S)
#define HP_SYSTEM_GMAC1_PAD_BIST_RCNT_V  0x0000003FU
#define HP_SYSTEM_GMAC1_PAD_BIST_RCNT_S  0

/** HP_SYSTEM_CPU_PWAIT_MODE_REG register
 *  Indicate status of core0 and core1 pwait
 */
#define HP_SYSTEM_CPU_PWAIT_MODE_REG (DR_REG_HP_SYS_BASE + 0x338)
/** HP_SYSTEM_CPU_PWAIT_MODE : RO; bitpos: [1:0]; default: 0;
 *  Indicate status of core0 and core1 pwait
 */
#define HP_SYSTEM_CPU_PWAIT_MODE    0x00000003U
#define HP_SYSTEM_CPU_PWAIT_MODE_M  (HP_SYSTEM_CPU_PWAIT_MODE_V << HP_SYSTEM_CPU_PWAIT_MODE_S)
#define HP_SYSTEM_CPU_PWAIT_MODE_V  0x00000003U
#define HP_SYSTEM_CPU_PWAIT_MODE_S  0

#ifdef __cplusplus
}
#endif
